Abstract: Embodiments of the present disclosure include methods and apparatuses utilized to reduce residual film layers from a substrate periphery region, such as an edge or bevel of the substrate. Contamination of the substrate bevel, backside and substrate periphery region may be reduced after a plasma process. In one embodiment, an edge ring includes a base circular ring having an inner surface defining a center opening formed thereon and an outer surface defining a perimeter of the base circular ring. The base circular ring includes an upper body and a lower portion connected to the upper body. A step is formed at the inner surface of the base circular ring and above a first upper surface of the upper body. The step defines a pocket above the first upper surface of the upper body. A plurality of raised features formed on the first upper surface of the base circular ring.

Abstract: Embodiments of the present disclosure include methods and apparatuses utilized to reduce residual film layers from a substrate periphery region, such as an edge or bevel of the substrate. Contamination of the substrate bevel, backside and substrate periphery region may be reduced after a plasma process. In one embodiment, an edge ring includes a base circular ring having an inner surface defining a center opening formed thereon and an outer surface defining a perimeter of the base circular ring. The base circular ring includes an upper body and a lower portion connected to the upper body. A step is formed at the inner surface of the base circular ring and above a first upper surface of the upper body. The step defines a pocket above the first upper surface of the upper body. A plurality of raised features formed on the first upper surface of the base circular ring.

Abstract: The present disclosure provides methods for etching through-silicon vias (TSVs) in a substrate. The method employs a cyclic polymer passivation layer deposition, depassivation process and plasma etching process. By alternating the duration performed in the plasma etching process and the polymer passivation deposition process during the TSVs formation process, a good sidewall profile and via depth control may be obtained.

Abstract: In some embodiments, a method for etching features into a substrate may include exposing a substrate having a photoresist layer disposed atop the substrate to a first process gas to form a polymer containing layer atop sidewalls and a bottom of a feature formed in the photoresist layer, wherein the first process gas is selectively provided to a first area of the substrate via a first set of gas nozzles disposed within a process chamber and; exposing the substrate to a second process gas having substantially no oxygen to etch the feature into the substrate, wherein the second process gas is selectively provided to a second area of the substrate via a second set of gas nozzles disposed in the process chamber.

Abstract: The present disclosure provides methods for via reveal etching process to form through-silicon vias (TSVs) in a substrate. In one embodiment, a method for performing a via reveal process to form through-silicon vias in a substrate includes providing a substrate having partial through-silicon vias formed from a first surface of the substrate into a processing chamber, wherein the partial through-silicon vias formed in the substrate are blind vias, supplying an etching gas mixture including at least a fluorine containing gas and a chlorine containing gas into the processing chamber, and preferentially removing a portion of the substrate from a second surface of the substrate to expose the through-silicon vias until a desired length of the through-silicon vias is exposed from the second surface of the substrate.

Abstract: Embodiments of the invention generally relate to an apparatus and method for plasma etching. In one embodiment, the apparatus includes a process ring with an annular step away from an inner wall of the ring and is disposed on a substrate support in a plasma process chamber. A gap is formed between the process ring and a substrate placed on the substrate support. The annular step has an inside surface having a height ranging from about 3 mm to about 6 mm. During operation, an edge-exclusion gas is introduced to flow through the gap and along the inside surface, so the plasma is blocked from entering the space near the edge of the substrate.

Abstract: The present disclosure provides methods for etching through-silicon vias (TSVs) in a substrate. The method employs a cyclic polymer passivation layer deposition, depassivation process and plasma etching process. By alternating the duration performed in the plasma etching process and the polymer passivation deposition process during the TSVs formation process, a good sidewall profile and via depth control may be obtained.