Abstract: Embodiments of the methods and systems of the present invention may provide improved methods for the verification of an integrated circuit where a verification project for an integrated circuit may be created by selecting a set of intent units corresponding to the integrated circuit design from a library of intent units and linking these intent units to the integrated circuit design. Specifically, in one embodiment each of these intent units may comprise a corresponding code component and text component such that from the set of intent units selected and configured based on the integrated circuit design a verification plan can be generated from the text components of the corresponding intent units while a testbench can be generated from the code components of the corresponding intent units. This testbench can then be used to generate a model for testing the integrated circuit design.

Abstract: A system and method for providing correlation of HDL signal names in the structural gate level description. In one embodiment, an HDL behavioral description of a circuit is processed by a correlation compiler to identify intermediate signals. The behavioral description is modified to specify that the intermediate signals are primary outputs of the circuit. The modified behavioral description is then processed by a synthesis tool to generate a structural description corresponding to the modified behavioral description. The structural description includes as outputs the identified intermediate signals.

Abstract: A system and method for providing correlation of HDL signal names in the structural gate level description. In one embodiment, an HDL behavioral description of a circuit is processed by a correlation compiler to identify intermediate signals. The behavioral description is modified to specify that the intermediate signals are primary outputs of the circuit. The modified behavioral description is then processed by a synthesis tool to generate a structural description corresponding to the modified behavioral description. The structural description includes as outputs the identified intermediate signals.

Abstract: A system and method for providing correlation of HDL signal names in the structural gate level description. In one embodiment, an HDL behavioral description of a circuit is processed by a correlation compiler to identify intermediate signals. The behavioral description is modified to specify that the intermediate signals are primary outputs of the circuit. The modified behavioral description is then processed by a synthesis tool to generate a structural description corresponding to the modified behavioral description. The structural description includes as outputs the identified intermediate signals.

Abstract: A system and method for providing encapsulation of HDL descriptions at the processes level includes a computer which accesses an Process Encapsulation computer program stored in computer memory. A computer processor which is electrically connected to the computer memory executes the Process Encapsulation computer program to encapsulate HDL processes as independent HDL objects within the structure of an HDL behavioral description.

Abstract: A system and method for providing correlation of HDL signal names in the structural gate level description. In one embodiment, an HDL behavioral description of a circuit is processed by a correlation compiler to identify intermediate signals. The behavioral description is modified to specify that the intermediate signals are primary outputs of the circuit. The modified behavioral description is then processed by a synthesis tool to generate a structural description corresponding to the modified behavioral description. The structural description includes as outputs the identified intermediate signals.