Abstract: Described are embodiments of methods for determining physiological data, such as vital signs, by using an optical diagnostic sensor, the method comprising receiving at a semiconductor material, which is located between a photodiode and a trench, an opening into silicon, or a backside wafer-level package (WLP) coating, light of a first wavelength and light of a second wavelength that are above the wavelength of red light, the semiconductor material acting as a filter that blocks wavelengths below the wavelength of red light; detecting, at the photodiode, light of at least one of the first wavelength or the second wavelength; and using the detected light to determine a vital sign.

Abstract: Apparatus, systems, and methods described herein may couple a base component associated with a portable electronic device (PED) to a display component associated with the PED such that the display component is capable of sliding and rotating relative to the base component. Other embodiments may be described and claimed.

Abstract: In some embodiments, a controller detects a board coupling condition and performs a shutdown in response to the board coupling condition. Other embodiments are described and claimed.

Abstract: Spacings between metal features are gap filled with HSQ. Portions of the deposited HSQ adjoining the side surfaces and upper surface of a metal feature are selectively heated to increase the density and etch resistance of the adjoining HSQ portions, thereby enabling formation of reliable, voidless, low resistance, borderless vias. In an embodiment of the present invention, selective heating is effected by heating a metal line to indirectly heat the adjoining portions of the HSQ layer, as by infrared heating.

Abstract: High integrity borderless vias are formed with a protective sidewall spacer on the exposed side surface of the underlying metal feature before depositing a barrier layer. Embodiments include depositing a dielectric capping layer on a metal feature having an ARC, e.g., TiN, etching to form a through-hole stopping on the capping layer, and then etching the exposed capping layer to form the protective sidewall spacer. Other embodiments include depositing a hard inorganic mask layer on the upper surface of the metal feature before depositing the capping layer, forming the through-hole, and sequentially etching the exposed capping layer to form the protective sidewall spacer and then the inorganic hard mask layer. Further embodiments include metal features without an ARC and retaining the inorganic mask layer on the upper surface of the metal feature.

Abstract: In a system having a PCI bus, an additional memory attached to the bus to allow a higher speed of data transfer for a number of copies from the computer to a number of devices. The additional memory has a number of DMA channels, each associated with an I/O device. One copy of the data required by an I/O device is transferred to the memory at normal computer FIFO speed. Thereafter, multiple copies of that data can be transferred to the I/O device from the memory at the higher data bus speed.

Abstract: Vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer. Embodiments include depositing a dielectric interlayer and forming a misaligned through-hole therein by etching. The dielectric material of the sidewall spacer and dielectric material of the dielectric interlayer are different. The etchant employed to form the through-hole exhibits a high selectivity with respect to the sidewall spacer material. The dielectric mask layer enables the formation of a sidewall spacer extending above the metal feature such that, after etching to form the misaligned through-hole, the sidewall spacer covers the side surface of the metal feature.

Abstract: Borderless submicron vias are formed between patterned metal layers gap filled with a high density plasma oxide. Heat treatment is conducted after chemical vapor deposition of the high density plasma oxide to substantially increase the grain size of the patterned metal layers, thereby improving electromigration resistance.

Abstract: High integrity borderless vias are formed with a protective sidewall spacer on the exposed side surface of the underlying metal feature before depositing a barrier layer. Embodiments include depositing a dielectric capping layer on a metal feature having an ARC, e.g., TiN, etching to form a through-hole stopping on the capping layer, and then etching the exposed capping layer to form the protective sidewall spacer. Other embodiments include depositing a hard inorganic mask layer on the upper surface of the metal feature before depositing the capping layer, forming the through-hole, and sequentially etching the exposed capping layer to form the protective sidewall spacer and then the inorganic hard mask layer. Further embodiments include metal features without an ARC and retaining the inorganic mask layer on the upper surface of the metal feature.

Abstract: Spacings between metal features are gap filled with HSQ. Portions of the deposited HSQ adjoining the side surfaces and upper surface of a metal feature are selectively heated to increase the density and etch resistance of the adjoining HSQ portions, thereby enabling formation of reliable, voidless, low resistance, borderless vias. In an embodiment of the present invention, selective heating is effected by heating a metal line to indirectly heat the adjoining portions of the HSQ layer, as by infrared heating.

Abstract: A patterned metal layer is gap filled with HSQ, an oxide formed thereon by PECVD, e.g., silicon dioxide derived from silane and N.sub.2 O, and planarized. The dielectric constant of the HSQ layer is minimized by baking the deposited HSQ layer in an inert atmosphere, e.g., N.sub.2, before heat soaking in an N.sub.2 O-containing atmosphere for no more than about 10 seconds and subsequent PECVD.

Abstract: Patterned metal layers are gap filled with HSQ and heat soaked in an oxidizing environment prior to oxide deposition by PECVD and planarization. Heat soaking is confined to less than about 10 seconds to minimize the dielectric constant of the HSQ layer.

Abstract: A single chamber of a vapor deposition system is used to deposit both Ti and TiN. A Ti layer is deposited on the sample using a noncollimated process. N.sub.2 gas is then introduced in the chamber. A TiN layer is then deposited over the Ti layer. A second Ti layer is deposited over the TiN layer. A separate Ti pasting of a TiN chamber is eliminated, thereby increasing throughput. Further, only three physical vapor deposition chambers are used, thereby allowing the fourth chamber to be used for other metal deposition. Moreover, the second Ti layer eliminates the first wafer effect and reduces sheet resistance relative to a same chamber Ti/TiN underlayer. Lastly, the Al deposited on this new stack has a stronger <111> crystallographic texture, which leads to better electromigration resistance.