Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

Abstract: A method and information processing system manage load and store operations that can be executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag, the load instruction becomes dependent upon all store instructions associated with a substantially similar hazard indicating flag.

Abstract: A load request is received to retrieve a piece of data from a location in memory and the load request follows one or more store requests in a set of instructions to store a piece of data in the location in memory. One or more possible locations in a cache for a piece of data corresponding to the location in memory is determined. Each possible location of the one or more possible locations in the cache is determined. It is then determined if at least one location of the one or more possible locations contains data to be stored in the location in memory. Data in one location of the at least one location is loaded, the data in the one location is from a store request of the one or more store requests and the store request is closest in the set of instructions to the load request.

Abstract: Embodiments relate to load queue entry reuse for operand store compare (OSC) history table update. An aspect includes allocating a load queue entry in a load queue to a load instruction that is issued into an instruction pipeline, the load queue entry comprising a valid tag that is set and a keep tag that is unset. Another aspect includes based on the flushing of the load instruction, unsetting the valid tag and setting the keep tag. Another aspect includes reissuing the load instruction into the instruction pipeline. Another aspect includes based on determining that the allocated load queue entry corresponds to the reissued load instruction, setting the valid tag and leaving the keep tag set. Another aspect includes based on completing the reissued load instruction, and based on the valid tag and the keep tag being set, updating the OSC history table corresponding to the load instruction.

Abstract: Embodiments relate to load queue entry reuse for operand store compare (OSC) history table update. An aspect includes allocating a load queue entry in a load queue to a load instruction that is issued into an instruction pipeline, the load queue entry comprising a valid tag that is set and a keep tag that is unset. Another aspect includes based on the flushing of the load instruction, unsetting the valid tag and setting the keep tag. Another aspect includes reissuing the load instruction into the instruction pipeline. Another aspect includes based on determining that the allocated load queue entry corresponds to the reissued load instruction, setting the valid tag and leaving the keep tag set. Another aspect includes based on completing the reissued load instruction, and based on the valid tag and the keep tag being set, updating the OSC history table corresponding to the load instruction.

Abstract: A queue management capability enables allocation and management of tracking queue entries, such as load and/or store queue entries, at execution time. By introducing execution-time allocation of load/store queue entries, the allocation point of those entries is delayed further into the execution stage of the instruction pipeline, reducing the overall time the entry remains allocated to a specific instruction. The queue management capability may also resolve deadlock conditions resulting from execution-time allocation of the queue entries and/or provide a mechanism to avoid such deadlock conditions.

Abstract: A load request is received to retrieve a piece of data from a location in memory and the load request follows one or more store requests in a set of instructions to store a piece of data in the location in memory. One or more possible locations in a cache for a piece of data corresponding to the location in memory is determined. Each possible location of the one or more possible locations in the cache is determined. It is then determined if at least one location of the one or more possible locations contains data to be stored in the location in memory. Data in one location of the at least one location is loaded, the data in the one location is from a store request of the one or more store requests and the store request is closest in the set of instructions to the load request.

Abstract: A load request is received to retrieve a piece of data from a location in memory and the load request follows one or more store requests in a set of instructions to store a piece of data in the location in memory. One or more possible locations in a cache for a piece of data corresponding to the location in memory is determined. Each possible location of the one or more possible locations in the cache is determined. It is then determined if at least one location of the one or more possible locations contains data to be stored in the location in memory. Data in one location of the at least one location is loaded, the data in the one location is from a store request of the one or more store requests and the store request is closest in the set of instructions to the load request.

Abstract: A load request is received to retrieve a piece of data from a location in memory and the load request follows one or more store requests in a set of instructions to store a piece of data in the location in memory. One or more possible locations in a cache for a piece of data corresponding to the location in memory is determined. Each possible location of the one or more possible locations in the cache is determined. It is then determined if at least one location of the one or more possible locations contains data to be stored in the location in memory. Data in one location of the at least one location is loaded, the data in the one location is from a store request of the one or more store requests and the store request is closest in the set of instructions to the load request.

Abstract: As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.

Abstract: As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.

Abstract: As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.

Abstract: In one embodiment, a computer-implemented method includes requesting, by a first processor thread of a computer processor, access to exception tracking logic. The exception tracking logic is accessible by two or more processor threads. The first processor thread receives access to the exception tracking logic. The first processor thread executes a process in slow mode. Based on detecting an exception in slow mode, the first processor thread stores, in the exception tracking logic, exception information about the exception. The exception information is copied from the exception tracking logic to a set of external registers outside the exception tracking logic. The exception tracking logic is released to allow access to the exception tracking logic by other processor threads of the two or more processor threads.

Abstract: Embodiments relate to a method, system and computer program product for storing a system-absolute address (SAA) in a first level look-aside buffer (TLB). In one embodiment, the system includes a central processor including the TLB and general purpose registers (GPRS). The TLB is configured for storing the SAA. The central processor is configured for issuing a load system-absolute address (LSAA) instruction. The system includes a translation unit that is in communication with the TLB of the central processor. The system is configured to perform a method including determining, based on the LSAA instruction being issued, whether the SAA is stored in the TLB. The method includes sending a translation request to the translation unit from the central processor based on the SAA not being stored in the TLB. The method includes determining the SAA by the translation unit based on receiving the translation request.

Abstract: Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.

Abstract: Techniques for generating a design structure for cache power reduction are described herein. In one example, a system includes logic to detect memory address information corresponding to accessed data in a first instruction, and detect memory address information corresponding to accessed data in a second instruction. The logic can also compare the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detect, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. The logic can also execute the second instruction using the accessed data from the first instruction.

Abstract: A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises detecting memory address information corresponding to accessed data in a first instruction, and detecting memory address information corresponding to accessed data in a second instruction. The method further comprises comparing the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detecting, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. In addition the method comprise executing the second instruction using the accessed data from the first instruction and detecting an error from the execution of the second instruction.

Abstract: In one embodiment, a computer-implemented method includes requesting, by a first processor thread of a computer processor, access to exception tracking logic. The exception tracking logic is accessible by two or more processor threads. The first processor thread receives access to the exception tracking logic. The first processor thread executes a process in slow mode. Based on detecting an exception in slow mode, the first processor thread stores, in the exception tracking logic, exception information about the exception. The exception information is copied from the exception tracking logic to a set of external registers outside the exception tracking logic. The exception tracking logic is released to allow access to the exception tracking logic by other processor threads of the two or more processor threads.

Abstract: Execution of threads in a processor core is controlled. The processor core supports simultaneous multi-threading (SMT) such that there can be effectively multiple logical central processing units (CPUs) operating simultaneously on the same physical processor hardware. Each of these logical CPUs is considered a thread. In such a multi-threading environment, it may be desirous for one thread to stop other threads on the processor core from executing. This may be in response to running a critical sequence or other sequence that needs the processor core resources or is manipulating processor core resources in a way that other threads would interfere with its execution.

Abstract: A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.