Patents by Inventor Khashayar Babaei Gavan

Khashayar Babaei Gavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11495490
    Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: November 8, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koichi Yatsuda, Tatsuya Yamaguchi, Yannick Feurprier, Frederic Lazzarino, Jean-Francois de Marneffe, Khashayar Babaei Gavan
  • Publication number: 20210118727
    Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Inventors: Koichi YATSUDA, Tatsuya YAMAGUCHI, Yannick FEURPRIER, Frederic LAZZARINO, Jean-Francois de MARNEFFE, Khashayar BABAEI GAVAN
  • Patent number: 10910259
    Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 2, 2021
    Assignees: TOKYO ELECTRON LIMITED, IMEC VZW
    Inventors: Koichi Yatsuda, Tatsuya Yamaguchi, Yannick Feurprier, Frederic Lazzarino, Jean-Francois de Marneffe, Khashayar Babaei Gavan
  • Patent number: 10493378
    Abstract: A method for producing a structure including, on a main surface of a substrate, at least one elongated cavity having openings at opposing ends. The method includes providing a substrate having a main surface. On the main surface, a first pair of features are formed that protrude perpendicularly from the main surface. The features have elongated sidewalls and a top surface, are parallel to one another, are separated by a gap having a width s1 and a bottom area, and have a width w1 and a height h1. At least the main surface of the substrate and the first pair of features are brought in contact with a liquid, suitable for making a contact angle of less than 90° with the material of the elongated sidewalls and subsequently the substrate is dried.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: December 3, 2019
    Assignee: IMEC VZW
    Inventors: Zheng Tao, Boon Teik Chan, XiuMei Xu, Khashayar Babaei Gavan, Efrain Altamirano Sanchez
  • Publication number: 20190181039
    Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Inventors: Koichi YATSUDA, Tatsuya YAMAGUCHI, Yannick FEURPRIER, Frederic LAZZARINO, Jean-Francois de MARNEFFE, Khashayar BABAEI GAVAN
  • Publication number: 20180043283
    Abstract: A method for producing a structure including, on a main surface of a substrate, at least one elongated cavity having openings at opposing ends. The method includes providing a substrate having a main surface. On the main surface, a first pair of features are formed that protrude perpendicularly from the main surface. The features have elongated sidewalls and a top surface, are parallel to one another, are separated by a gap having a width s1 and a bottom area, and have a width w1 and a height h1. At least the main surface of the substrate and the first pair of features are brought in contact with a liquid, suitable for making a contact angle of less than 90° with the material of the elongated sidewalls and subsequently the substrate is dried.
    Type: Application
    Filed: August 10, 2017
    Publication date: February 15, 2018
    Applicant: IMEC VZW
    Inventors: Zheng Tao, Boon Teik Chan, XiuMei Xu, Khashayar Babaei Gavan, Efrain Altamirano Sanchez