Patents by Inventor Khasim S. Dudekula

Khasim S. Dudekula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11936915
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20230134137
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: December 28, 2022
    Publication date: May 4, 2023
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 11546639
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20220021906
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 20, 2022
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 11172233
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20210014538
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 10863204
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20200107046
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 10440395
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 9560382
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20170013282
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 9369735
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: June 14, 2016
    Assignee: Intel Corporation
    Inventors: Jorge E Caviedes, Mahesh Subedar, Khasim S Dudekula
  • Patent number: 9020046
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: April 28, 2015
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20140050268
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: August 6, 2013
    Publication date: February 20, 2014
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 8520739
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mehesh M. Subedar, Khasim S. Dudekula