Patents by Inventor Khay Chwan Saw
Khay Chwan Saw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11569196Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.Type: GrantFiled: August 26, 2021Date of Patent: January 31, 2023Assignee: Infineon Technologies AGInventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
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Patent number: 11296000Abstract: An electronic circuit includes a first packaged semiconductor device having a first semiconductor die including a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound.Type: GrantFiled: July 15, 2020Date of Patent: April 5, 2022Assignee: Infineon Technologies AGInventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
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Patent number: 11274984Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.Type: GrantFiled: June 2, 2020Date of Patent: March 15, 2022Assignee: INFINEON TECHNOLOGIES AGInventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw
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Publication number: 20210391298Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.Type: ApplicationFiled: August 26, 2021Publication date: December 16, 2021Inventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
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Patent number: 11133281Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.Type: GrantFiled: April 4, 2019Date of Patent: September 28, 2021Assignee: Infineon Technologies AGInventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
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Publication number: 20210025774Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.Type: ApplicationFiled: June 2, 2020Publication date: January 28, 2021Inventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw
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Publication number: 20200350222Abstract: An electronic circuit includes a first packaged semiconductor device having a first semiconductor die including a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound.Type: ApplicationFiled: July 15, 2020Publication date: November 5, 2020Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
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Publication number: 20200321269Abstract: A semiconductor package includes an electrically insulating first encapsulant body having an upper surface, a first semiconductor die encapsulated within the first encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the first encapsulant body, a plurality of electrically conductive leads, each of the leads having interior ends that are encapsulated within the first encapsulant body and outer ends that are exposed from the first encapsulant body, and a first direct electrical connection between the first conductive pad and the interior end of a first lead from the plurality. The first direct electrical connection includes a first conductive track formed in the upper surface of the first encapsulant body. The first encapsulant body includes a laser activatable mold compound. The first conductive track is formed in a first laser activated region of the laser activatable mold compound.Type: ApplicationFiled: May 15, 2019Publication date: October 8, 2020Inventors: Chau Fatt Chiang, Khay Chwan Saw
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Publication number: 20200321276Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.Type: ApplicationFiled: April 4, 2019Publication date: October 8, 2020Inventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
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Patent number: 10796981Abstract: A semiconductor package includes an electrically insulating first encapsulant body having an upper surface, a first semiconductor die encapsulated within the first encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the first encapsulant body, a plurality of electrically conductive leads, each of the leads having interior ends that are encapsulated within the first encapsulant body and outer ends that are exposed from the first encapsulant body, and a first direct electrical connection between the first conductive pad and the interior end of a first lead from the plurality. The first direct electrical connection includes a first conductive track formed in the upper surface of the first encapsulant body. The first encapsulant body includes a laser activatable mold compound. The first conductive track is formed in a first laser activated region of the laser activatable mold compound.Type: GrantFiled: May 15, 2019Date of Patent: October 6, 2020Assignee: Infineon Technologies AGInventors: Chau Fatt Chiang, Khay Chwan Saw
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Patent number: 10741466Abstract: A first packaged semiconductor device is provided. The first packaged semiconductor device includes a first semiconductor die having a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound. Forming the conductive track includes activating a portion of the outer surface of the first mold compound for an electroless plating process, and performing the electroless plating process so as to form an electrically conductive material only within the activated portion of the outer surface of the first mold compound.Type: GrantFiled: November 17, 2017Date of Patent: August 11, 2020Assignee: Infineon Technologies AGInventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
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Publication number: 20200051898Abstract: In an embodiment, a leadframe includes a first electrically conductive part and a second electrically conductive part, each having an outer surface arranged to provide substantially coplanar outer contact areas having a footprint and an inner surface opposing the outer surface, the first part being spaced apart from the second part by a gap, a first recess arranged in the inner surface of the first part, a second recess arranged in the inner surface of the second part, and a first electrically conductive insert that is arranged in, and extends between, the first recess and the second recess and bridges the gap between the first part and the second part.Type: ApplicationFiled: August 6, 2019Publication date: February 13, 2020Inventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Kok Yau Chua, Josef Hoeglauer, Swee Kah Lee, Khay Chwan Saw
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Patent number: 10325837Abstract: A semiconductor package includes a semiconductor die embedded in a molded package body, leads electrically connected to the die and protruding from a side face of the molded package body, and a recess extending inward from the side face and into a bottom main face of the molded package body to forma single groove. The recess begins below a region of the side face from which the leads protrude, so that this region of the side face is flat and each of the leads exits the molded package body in the same plane. A first subset of the leads is bent inward towards the molded package body and seated in the single groove, to form a first row of leads configured for surface mounting. A second subset of the leads extends outward from the molded package body, to form a second row of leads configured for surface mounting.Type: GrantFiled: November 7, 2017Date of Patent: June 18, 2019Assignee: Infineon Technologies AGInventors: Cher Hau Danny Koh, Hai Sin Chong, Stefan Machiener, Yong Chern Poh, Toni Salminen, Khay Chwan Saw
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Publication number: 20190157173Abstract: A first packaged semiconductor device is provided. The first packaged semiconductor device includes a first semiconductor die having a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound. Forming the conductive track includes activating a portion of the outer surface of the first mold compound for an electroless plating process, and performing the electroless plating process so as to form an electrically conductive material only within the activated portion of the outer surface of the first mold compound.Type: ApplicationFiled: November 17, 2017Publication date: May 23, 2019Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
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Publication number: 20190139869Abstract: A semiconductor package includes a semiconductor die embedded in a molded package body, leads electrically connected to the die and protruding from a side face of the molded package body, and a recess extending inward from the side face and into a bottom main face of the molded package body to form a single groove. The recess begins below a region of the side face from which the leads protrude, so that this region of the side face is flat and each of the leads exits the molded package body in the same plane. A first subset of the leads is bent inward towards the molded package body and seated in the single groove, to form a first row of leads configured for surface mounting. A second subset of the leads extends outward from the molded package body, to form a second row of leads configured for surface mounting.Type: ApplicationFiled: November 7, 2017Publication date: May 9, 2019Inventors: Cher Hau Danny Koh, Hai Sin Chong, Stefan Macheiner, Yong Chern Poh, Toni Salminen, Khay Chwan Saw