Patents by Inventor Khay Chwan Saw

Khay Chwan Saw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11569196
    Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: January 31, 2023
    Assignee: Infineon Technologies AG
    Inventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
  • Patent number: 11296000
    Abstract: An electronic circuit includes a first packaged semiconductor device having a first semiconductor die including a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: April 5, 2022
    Assignee: Infineon Technologies AG
    Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
  • Patent number: 11274984
    Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: March 15, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw
  • Publication number: 20210391298
    Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.
    Type: Application
    Filed: August 26, 2021
    Publication date: December 16, 2021
    Inventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
  • Patent number: 11133281
    Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: September 28, 2021
    Assignee: Infineon Technologies AG
    Inventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
  • Publication number: 20210025774
    Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.
    Type: Application
    Filed: June 2, 2020
    Publication date: January 28, 2021
    Inventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw
  • Publication number: 20200350222
    Abstract: An electronic circuit includes a first packaged semiconductor device having a first semiconductor die including a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound.
    Type: Application
    Filed: July 15, 2020
    Publication date: November 5, 2020
    Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
  • Publication number: 20200321269
    Abstract: A semiconductor package includes an electrically insulating first encapsulant body having an upper surface, a first semiconductor die encapsulated within the first encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the first encapsulant body, a plurality of electrically conductive leads, each of the leads having interior ends that are encapsulated within the first encapsulant body and outer ends that are exposed from the first encapsulant body, and a first direct electrical connection between the first conductive pad and the interior end of a first lead from the plurality. The first direct electrical connection includes a first conductive track formed in the upper surface of the first encapsulant body. The first encapsulant body includes a laser activatable mold compound. The first conductive track is formed in a first laser activated region of the laser activatable mold compound.
    Type: Application
    Filed: May 15, 2019
    Publication date: October 8, 2020
    Inventors: Chau Fatt Chiang, Khay Chwan Saw
  • Publication number: 20200321276
    Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.
    Type: Application
    Filed: April 4, 2019
    Publication date: October 8, 2020
    Inventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
  • Patent number: 10796981
    Abstract: A semiconductor package includes an electrically insulating first encapsulant body having an upper surface, a first semiconductor die encapsulated within the first encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the first encapsulant body, a plurality of electrically conductive leads, each of the leads having interior ends that are encapsulated within the first encapsulant body and outer ends that are exposed from the first encapsulant body, and a first direct electrical connection between the first conductive pad and the interior end of a first lead from the plurality. The first direct electrical connection includes a first conductive track formed in the upper surface of the first encapsulant body. The first encapsulant body includes a laser activatable mold compound. The first conductive track is formed in a first laser activated region of the laser activatable mold compound.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: October 6, 2020
    Assignee: Infineon Technologies AG
    Inventors: Chau Fatt Chiang, Khay Chwan Saw
  • Patent number: 10741466
    Abstract: A first packaged semiconductor device is provided. The first packaged semiconductor device includes a first semiconductor die having a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound. Forming the conductive track includes activating a portion of the outer surface of the first mold compound for an electroless plating process, and performing the electroless plating process so as to form an electrically conductive material only within the activated portion of the outer surface of the first mold compound.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
  • Publication number: 20200051898
    Abstract: In an embodiment, a leadframe includes a first electrically conductive part and a second electrically conductive part, each having an outer surface arranged to provide substantially coplanar outer contact areas having a footprint and an inner surface opposing the outer surface, the first part being spaced apart from the second part by a gap, a first recess arranged in the inner surface of the first part, a second recess arranged in the inner surface of the second part, and a first electrically conductive insert that is arranged in, and extends between, the first recess and the second recess and bridges the gap between the first part and the second part.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 13, 2020
    Inventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Kok Yau Chua, Josef Hoeglauer, Swee Kah Lee, Khay Chwan Saw
  • Patent number: 10325837
    Abstract: A semiconductor package includes a semiconductor die embedded in a molded package body, leads electrically connected to the die and protruding from a side face of the molded package body, and a recess extending inward from the side face and into a bottom main face of the molded package body to forma single groove. The recess begins below a region of the side face from which the leads protrude, so that this region of the side face is flat and each of the leads exits the molded package body in the same plane. A first subset of the leads is bent inward towards the molded package body and seated in the single groove, to form a first row of leads configured for surface mounting. A second subset of the leads extends outward from the molded package body, to form a second row of leads configured for surface mounting.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 18, 2019
    Assignee: Infineon Technologies AG
    Inventors: Cher Hau Danny Koh, Hai Sin Chong, Stefan Machiener, Yong Chern Poh, Toni Salminen, Khay Chwan Saw
  • Publication number: 20190157173
    Abstract: A first packaged semiconductor device is provided. The first packaged semiconductor device includes a first semiconductor die having a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound. Forming the conductive track includes activating a portion of the outer surface of the first mold compound for an electroless plating process, and performing the electroless plating process so as to form an electrically conductive material only within the activated portion of the outer surface of the first mold compound.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 23, 2019
    Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
  • Publication number: 20190139869
    Abstract: A semiconductor package includes a semiconductor die embedded in a molded package body, leads electrically connected to the die and protruding from a side face of the molded package body, and a recess extending inward from the side face and into a bottom main face of the molded package body to form a single groove. The recess begins below a region of the side face from which the leads protrude, so that this region of the side face is flat and each of the leads exits the molded package body in the same plane. A first subset of the leads is bent inward towards the molded package body and seated in the single groove, to form a first row of leads configured for surface mounting. A second subset of the leads extends outward from the molded package body, to form a second row of leads configured for surface mounting.
    Type: Application
    Filed: November 7, 2017
    Publication date: May 9, 2019
    Inventors: Cher Hau Danny Koh, Hai Sin Chong, Stefan Macheiner, Yong Chern Poh, Toni Salminen, Khay Chwan Saw