Abstract: A wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core itself is a silver-based wire core, wherein the coating layer is a double-layer comprised of a 1 to 100 nm thick inner layer of nickel or palladium and an adjacent 1 to 250 nm thick outer layer of gold, characterized in that the wire exhibits a total carbon content of ?40 wt.-ppm.

Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.

Abstract: Methods of characterizing a mechanical stress level in a stressed layer of a transistor and a mechanical stress characterizing test structure are disclosed. In one embodiment, the test structure includes a first test transistor including a first stress level; and at least one second test transistor having a substantially different second stress level. A testing circuit can then be used to characterize the mechanical stress level by comparing performance of the first test transistor and the at least one second test transistor. The type of test structure depends on the integration scheme used. In one embodiment, at least one second test transistor is provided with a substantially neutral stress level and/or an opposite stress level from the first stress level. The substantially neutral stress level may be provided by either rotating the transistor, removing the stressed layer causing the stress level or de-stressing the stressed layer causing the stress layer.

Abstract: A meter for measuring the turbidity of a fluid includes a light source for directing a light beam through a fluid under test towards a reflective surface and a sensor for detecting light reflected from the reflective surface and passing back through the fluid under test. The meter outputs a signal indicative of the turbidity of the fluid under test.

Abstract: In one embodiment, apparatus for characterizing a target is provided with a plurality of light sources that are positioned to illuminate a target. The light sources emit different wavelengths of light. A color sensor is positioned to receive and sense different wavelengths of light reflected from the target. A control system is operably associated with the plurality of light sources and the color sensor to A) in a calibration mode, operate the light sources and separately regulate drive signals of light sources emitting different wavelengths of light, in response to outputs of the color sensor, and B) in an operational mode, i) operate the light sources using the regulated drive signals, and ii) characterize the target in response to data output from the color sensor. A textile characterization system is also disclosed.

Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

Abstract: An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.