Abstract: A data management method, a memory controller and an embedded memory storage apparatus are provided. The embedded memory storage apparatus has a plurality of physical blocks and each of the physical blocks has fast physical pages and slow physical pages. The method includes detecting a status of a state indication unit. The method further includes automatically reading data stored in the embedded memory storage apparatus, using the fast and slow physical pages of the embedded memory storage apparatus to re-store the data and marking status of the state indication unit as a second status when the status of the state indication unit is a first status. Accordingly, the storage space of the embedded memory storage apparatus can be efficiently used.

Abstract: A data management method, a memory controller and an embedded memory storage apparatus are provided. The embedded memory storage apparatus has a plurality of physical blocks and each of the physical blocks has fast physical pages and slow physical pages. The method includes detecting a status of a state indication unit. The method further includes automatically reading data stored in the embedded memory storage apparatus, using the fast and slow physical pages of the embedded memory storage apparatus to re-store the data and marking status of the state indication unit as a second status when the status of the state indication unit is a first status. Accordingly, the storage space of the embedded memory storage apparatus can be efficiently used.

Abstract: A system, a controller, and a method for data storage are provided. The system includes a first storage unit, a second storage unit, and a controller. The first storage unit comprises a single-layer structure for storing data, and the second storage unit comprises a multi-layer structure for storing data. The controller is coupled to the first storage unit, the second storage unit, and a host and controls the host to set the first storage unit as a master storage device and set the second storage unit as a slave storage device. As a result, the host can recognize the first storage unit and the second storage unit as two independent storage devices for storing data. Thereby, the data storage process can be simplified.

Abstract: A flash storage chip including a single circuit board, a microcontroller, a flash memory, and a peripheral component interconnect express (PCI Express) connecting interface is provided. The microcontroller, the flash memory, and the PCI Express connecting interface are embedded on the single circuit board, and the microcontroller has a flash memory interface and a PCI Express interface. When a host writes a data into the flash storage chip, the microcontroller receives the data though the PCI Express interface and stores the data into the flash memory though the flash memory interface. When the host reads a data form the flash storage chip, the microcontroller reads the data from the flash memory though the flash memory interface and transmits the data to the host though the PCI Express interface and the PCI Express connecting interface.

Abstract: A system, a controller, and a method for data storage are provided. The system includes a first storage unit, a second storage unit, and a controller. The first storage unit comprises a single-layer structure for storing data, and the second storage unit comprises a multi-layer structure for storing data. The controller is coupled to the first storage unit, the second storage unit, and a host and controls the host to set the first storage unit as a master storage device and set the second storage unit as a slave storage device. As a result, the host can recognize the first storage unit and the second storage unit as two independent storage devices for storing data. Thereby, the data storage process can be simplified.

Abstract: A solid state disk (SSD) storage system with a parallel accessing architecture, including a SSD controller and a plurality of transmission interfaces of a predetermined bit number and bandwidth, and a solid state disk controller thereof are provided. The SD controller forms channels for transmitting control signals and data with one or more flash memories through each of the transmission interfaces. That is, independent transmission channels are constituted between the SSD controller, the transmission interfaces with multiple bits, and the flash memories. In one embodiment, the transmission interfaces are compatible with MMC 4.0 protocol or higher. Moreover, a host controls and accesses the flash memories through a SATA bus interface and the SSD controller, and uses a direct memory access (DMA) engine with a bidirectional connection port in the SSD controller to transmit data.

Abstract: A flash memory and a method for utilizing the same are disclosed. The method for utilizing a flash memory includes the steps of: a) providing a flash memory of a single chip; b) formatting the flash memory and marking bad blocks of the flash memory as a bad-block area free of reliably saved data; c) calculating a capacity of an available memory with the flash memory, wherein the available memory excludes the bad-block area of the flash memory; and d) dividing the available memory into a first storing memory and a second storing memory, wherein the first storing memory and the second storing memory have different capacities.

Abstract: The present invention provides a palm type electrocardiograph having a case, in which a push button is provided at the front side thereof, a USB port is installed along a lateral side thereof, and two metal holes are assembled at the back thereof. A conductive sticker is also designed with two metal electrodes being penetrately assembled in the center thereon. The conductive sticker has three layers, the first layer is foam, the second layer is conductive graphite, and the third layer is conductive adhesive. An internal circuit is provided in the palm type electrocardiograph, including a microprocessor, an A/D converter, a program memory and a flash memory.

Abstract: The present invention discloses an integrating data processing system. The system includes a master device with a host interface for processing data, at least one NAND flash memory unit having a unit interface, and a flash memory controller. For controlling access to the NAND flash memory unit, the flash memory controller is provided with a first interface connected with the host interface of the master device, and a second interface connected with the unit interface of the NAND flash memory unit. The first interface is identical to the unit interface of the flash memory and the second interface is identical to the host interface of the master device. The master device can access the NAND flash memory unit via the flash memory controller thereby facilitating to fit in with the development of new flash memory device without upgrading the original master device.

Abstract: A method of providing a universal platform for an application program for use in a communication terminal is disclosed. Meanwhile, the method of providing a universal platform for an application program of communication terminals, includes the steps of: a) storing a virtual machine and an application program in a combo card; b) providing the combo card to each of the communication terminals; c) loading the virtual machine from the combo card; and d) executing the virtual machine to form the universal platform such that the application program can be performed in the communication terminals regardless of different operating systems of the communication terminals.

Abstract: An integrated SIM system for use with a communication terminal is disclosed. Meanwhile, the integrated subscriber identity module (SIM) system for use with a communication terminal includes a SIM unit for allowing communication between the communication terminal and an external base station; a memory module stored with a virtual machine (VM) for providing the communication terminal with a platform for various applications; and a controlling module for acting as an interface between the communication terminal and the SIM unit/memory module to access one of the SIM unit and the memory module.

Abstract: A flash storage chip including a single circuit board, a microcontroller, a flash memory, and a peripheral component interconnect express (PCI Express) connecting interface is provided. The microcontroller, the flash memory, and the PCI Express connecting interface are embedded on the single circuit board, and the microcontroller has a flash memory interface and a PCI Express interface. When a host writes a data into the flash storage chip, the microcontroller receives the data though the PCI Express interface and stores the data into the flash memory though the flash memory interface. When the host reads a data form the flash storage chip, the microcontroller reads the data from the flash memory though the flash memory interface and transmits the data to the host though the PCI Express interface and the PCI Express connecting interface.

Abstract: A universal serial bus (USB) memory system and a control method thereof are disclosed. The USB memory system includes a microprocessor, a storage unit in communication with the microprocessor, an interface unit in communication with the microprocessor, an audio device in communication with the microprocessor, and a sound output device in communication with the audio device. Moreover, the control method includes steps of a) automatically executing a program of a host system while the USB memory system is connected with the host system via the interface unit; b) selecting one of a MIDI and a chord signal as an audio signal via the program; c) transmitting the audio signal to the audio device; d) decoding the audio signal by the audio device and transmitting a resultant decoded sound signal to the sound output device; and e) outputting the decoded sound signal via the sound output device.

Abstract: A flash memory and a method for utilizing the same are disclosed. The method for utilizing a flash memory includes the steps of: a) providing a flash memory of a single chip; b) formatting the flash memory and marking bad blocks of the flash memory as a bad-block area free of reliably saved data; c) calculating a capacity of an available memory within the flash memory, wherein the available memory excludes the bad-block area of the flash memory; and d) dividing the available memory into a first storing memory and a second memory, wherein the first storing memory and the second storing memory have different capacities.

Abstract: A storage controlling and judging methods of flash memory is provided. According to an aspect of the present invention, the flash memory comprises plurality sets of mother and child blocks for temporarily saving the written data in order to increase the saving/retrieving speed of the flash memory. According to another aspect of the present invention, the correlation concept of the mother and child block is used to substantially reduce the erase frequency for extending the service life of the flash memory.

Abstract: A storage media with receiving digital TV and radio signal function is provided. The storage media comprises a digital TV signal module, a control device and a flash memory. The digital TV signal module comprises a receiver for receiving digital TV signal and a digital TV signal transmission interface. The control device comprises a digital TV signal transmission interface orderly connected to a microprocessor and a data transmission interface provided for connecting to an electronic device. The flash memory is electrically connected to the microprocessor of the control device.

Abstract: A storage controlling and judging methods of flash memory is provided. According to an aspect of the present invention, the flash memory comprises plurality sets of mother and child blocks for temporarily saving the written data in order to increase the saving/retrieving speed of the flash memory. According to another aspect of the present invention, the correlation concept of the mother and child block is used to substantially reduce the erase frequency for extending the service life of the flash memory.

Abstract: A method of writing data to a large block of a flash memory cell is disclosed. When the processor writes data to the flash memory cell, if the changed data can not fill up the whole page, the processor will pick a block from one of the backed up blocks in the flash memory cell using as a special block for storing changed data temporarily, and continue to write the next changed data into the special block until whole space in the page is filled up. When the page is completely filled, then the data stored temporarily in the special block is moved to a buffer of the backed up block and then the special block is erased so that it can be used as a back up block, thus when writing data to flash memory cell, even when the change of data is unable fully fill up the whole page, the changed data still can be written continuously, and therefore the writing speed can be substantially increased.

Abstract: A non-volatile memory storage integrated circuit is disclosed. The non-volatile memory storage integrated circuit of the present invention comprises a controlling IC, a NAND IC and a memory IC. The non-volatile memory storage integrated circuit of the present invention can be used as a basic I/O system for electronic devices.

Abstract: A method of writing data to a large block of a flash memory cell is disclosed. When the processor writes data to the flash memory cell, if the changed data can not fill up the whole page, the processor will pick a block from one of the backed up blocks in the flash memory cell using as a special block for storing changed data temporarily, and continue to write the next changed data into the special block until whole space in the page is filled up. When the page is completely filled, then the data stored temporarily in the special block is moved to a buffer of the backed up block and then the special block is erased so that it can be used as a back up block, thus when writing data to flash memory cell, even when the change of data is unable fully fill up the whole page, the changed data still can be written continuously, and therefore the writing speed can be substantially increased.