Abstract: A differential fuse circuit 10 is disclosed herein. A first fuse 12 and a second fuse 14 are coupled to a supply potential V.sub.DD (e.g., five volts). Circuitry 16 and 18 for blowing the two fuses 12 and 14 is also provided. A current mirror 46 including a first leg and a second leg is also provided. The current mirror 46 is designed so that a current through the first leg will induce a current in the second leg. The first leg is coupled between the first fuse 12 and a reference potential V.sub.SS and the second leg is coupled between the second fuse 14 and the reference potential V.sub.SS. An output node 56 is provided between the second fuse 14 and the second leg of the current mirror 46. A differential sense circuit 24 may also be included between the fuses 12 and 14 and the current mirror 46.

Abstract: In a semiconductor device, an on chip coaxial cable reduces noise from adversely affecting a signal transmitted by a signal conductor. The signal conductor lies within and is isolated from a second conductor. A dielectric, such as oxide, may provide isolation. In multi level metal devices, such as double level metal devices, the signal conductor can be formed of a first level of metal and a portion of the second conductor can be formed of the first level of metal also. After forming a first level of metal, it is patterned to separate the first signal conductor from a first conductive noise shield and a second conductive noise shield. A second level of metal and a conductive level of material such as polysilicon can complete formation of the second conductor. Oxide insulators can provide isolation between the signal conductor and the second conductor by lying between the top conductive noise shield and the signal conductor and by lying between the bottom conductive noise shield and the signal conductor.

Abstract: This dielectric relaxation correction circuit for charge-redistribution A/D converters, which has a comparator 20 and operates in a sample, hold and conversion mode, comprises: a capacitor array 22, a replica capacitance 35, having a bottom plate, arranged so as to be subject to the same sequence of charging voltages that the array capacitors 22 experience but in a neutralizing manner such that an error in the capacitor array 22 voltage is neutralized by the same error in the replica capacitance 35, and; a sample and hold circuit (S/H) 36 for sampling an input signal voltage during the sample mode, wherein the sample and hold 36 is arranged to hold the bottom plate of the replica capacitance 35 at the input signal voltage. Other devices, systems and methods are also disclosed.

Abstract: A capacitor array circuit is disclosed herein. A main capacitor array includes at least a most significant array portion 12 and a least significant array portion 14. A coupling capacitor C.sub.C is formed between the two portions of the array. Typically, one plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the least significant array portion 14 and a second plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the most significant array portion 12. A variable calibration capacitor C.sub.CAL is also provided. In a preferred embodiment, the variable calibration capacitor C.sub.CAL is coupled between the coupling capacitor C.sub.C and an AC ground node. In alternate embodiment, the variable calibration capacitor C.sub.CAL is coupled in parallel with the coupling capacitor C.sub.C. In the preferred embodiment, the variable calibration capacitor C.sub.

Abstract: An analog to digital converter system (10) is disclosed which comprises an SAR logic circuit (12) which controls capacitor array control switches (14) which themselves control a capacitor array (16). A top plate (18) of the capacitor array (18) is selectively coupled to a coarse comparator (24) and a fine comparator (26). The outputs of the coarse comparator (24) and the fine comparator (26) are input into an error correction circuit (28). In operation, the coarse comparator (24) is used to approximate a predetermined number of the most significant bits of the digital word to be output by the system (10) while the fine comparator (26) is used to approximate the remaining bits of the digital word. In this manner, the coarse comparator (24) alone is subjected to the high voltages which might cause errors as a results of the hysteresis effect in the threshold voltages of the MOSFETs used to construct the comparators.

Abstract: There is disclosed a fully differential converter (10) having a very high common mode rejection ratio. The capacitive parasitics (CP) are accounted for by a strategic placement of error correction capacitances (20). The actual value of the capacitance is calculated from time to time by successively making comparative circuit operations and by adding and subtracting capacitance automatically under logic control (62) until the circuit is in near balance. The final value of the added capacitance for any given calculation set is stored in a memory (61). In this manner the circuit become self-calibrating and common mode rejection ratios over 90 db are possible.

Abstract: An analog-to-digital converter and method which provides error correction is disclosed that eliminates the linear and quadratic error terms which arise through capacitor value dependence upon voltage.

Abstract: A system (10) is disclosed which tunes a result (14) of a process (12) relative to a reference (16). The system (10) uses two control parameters (C.sub.1 and C.sub.2) which are controlled by a switch (20). The control parameters (C.sub.1 and C.sub.2) are controlled such that only one of the two is acting upon the process (12) to alter the result (14) at any one time.

Abstract: An analog signal conditioning and digitizing integrated circuit is provided having a multiplying digital to analog converter means (MDAC) including a gain capacitor array and an offset capacitor array, an operational amplifier, a feedback circuit including a feedback capacitor and a feedback clamping transistor, the operational amplifier and feedback circuit connected to the gain and offset capacitor arrays for setting the gain and the amount of offset correction of the MDAC, a correlated double sample circuit including a series capacitor connected to the operational amplifier and a series clamping transistor connected to the junction of the series capacitor and a buffer amplifier for sampling the noise to be substracted and/or nulled across the series capacitor, and an analog to digital converter operatively connected to the MDAC for digitizing the output of the MDAC.

Abstract: A microprocessor system includes a CPU device with on-chip or off-chip memory, and data and control busses for accessing memory and/or peripherals. The peripheral circuitry includes one or more channels for input and/or output of data, wherein various characteristics of the treatment of data in the channel are controlled by the program being executed in the CPU. In one embodiment analog input and output channels are included, and the A-to-D or D-to-A conversion rates are selected by executing a data output instruction by the CPU. The cut-off points of the filters are likewise selected. The A-to-D converter loads a first-in first-out memory which is read by the CPU in burst mode when filled. Likewise, the CPU loads digital data to a first-in first-out memory in the output channel, and then the D-to-A converts at its selected rate.

Abstract: A method and apparatus is disclosed which corrects for errors produced in data acquisition systems. Disclosed is a method and circuit for correcting errors, such as mismatch between binary weighted capacitors and offset, in a charge redistribution, weighted capacitor array analog-to-digital converter. A self-calibrating, self-correcting circuit is comprised of a second binary array of capacitors which adds to the regular charge redistribution capacitor array an error correcting signal to compensate for the mismatch. This error correcting signal is then stored and the other error correcting signals for other capacitors in the regular capacitor array are determined and subsequently stored for later correction of other capacitance mismatch.