Abstract: There is provided an initialization signal generation apparatus for use in a semiconductor device. The apparatus comprises a voltage divider for dividing an external voltage into a plurality of divided voltages, a first initialization signal generator for producing a first initialization signal in response to a first divided voltage on a first node among the divided voltages, and a second initialization signal generator for providing a second initialization signal in response to a second divided voltage on a second node among the divided voltages.

Abstract: A power-on reset circuit senses levels of internal power voltage including a boosting voltage and a core voltage as well as an external power voltage, and outputs a power-on reset signal when the voltages are all over a predetermined level, thereby improving stability of an initializing operation. The power-on reset circuit comprises an external power voltage detecting unit, a plurality of internal power voltage detecting units and a selective output unit.

Abstract: Disclosed are a connecting method of a sense amplifier and a semiconductor memory device using the same. The semiconductor memory device comprises a memory cell array including a plurality of word lines connected respectively to a plurality of memory cell blocks, each of which is composed of a plurality of memory cells, in a row direction of the memory cells, and a plurality of pairs of bit lines connected respectively to the plurality of memory cell blocks in a column direction of the memory cells; and a plurality of sense amplifier arrays, each of which includes a plurality of sense amplifiers, each of which is connected to bit lines and complementary bit lines of the plurality of pairs of bit lines, for sensing a potential difference between the bit lines and the complementary bit lines.

Abstract: The present invention discloses a circuit for detecting a negative word line voltage including a detecting unit for detecting a negative word line voltage in a detection node by using a plurality of loads coupled in series between a power supply terminal and a negative word line voltage terminal, a test signal generating unit for generating a plurality of test signals for detecting variations of the negative word line voltage, and a control unit driven according to the test signals, for controlling a potential of the detection node by adjusting a number of the loads of the detecting unit. The circuit for detecting the negative word line voltage can detect a wanted level of negative word line voltage by using the plurality of test signals without modifying the circuit, to reduce a development period of DRAM semiconductor products.