Abstract: A power reduction system for a UART system having a controllable oscillator for producing free-running clock signals. A controlled clock synchronizer having an output terminal is coupled to the oscillator and responsive to both a first control signal thereto and application of the free-running clock signals thereto to provide synchronized pulses and is responsive to both a second control signal different from the first control signal thereto and application of the free-running clock signals thereto to cease production of the synchronized pulses at the output terminal. A UART core controls the oscillator and the clock synchronizer and is operated under control of clock signals from the clock synchronizer. The controllable oscillator includes an inverter having a feedback circuit thereacross including a switch responsive to the third control signal to cause the oscillator to cease oscillation.

Abstract: A processor on an add-on card that arbitrates demand on a memory unit on the add-on card. The processor and memory unit are used for the underlying functionality of the add-on card. The processor determines an appropriate time to allow interface operations to the memory unit when the memory unit is not already being accessed for the underlying functionality of the card. By using the processor and memory unit on the add-on card for interface operations to the host computer, the add-on interface circuitry on the add-on card can be minimized and simplified.

Abstract: An embodiment of the present invention is a digital circuit (block 12 of FIG.

Abstract: A glitch filter identifies and eliminates positive edge and negative edge glitches without utilizing a high frequency sampling clock. The glitch filter comprises a programmable delay buffer string, two multiple input AND gates and a latch. The buffer string provides a plurality of incrementally delayed signals and utilizes them as signal samples thus simulating a high frequency sampling clock. The two multiple input AND gates serve to eliminate positive or negative edge glitches. The latch outputs the accurate filtered data without any positive or negative edge glitches.

Abstract: A reference time signal generation system 10 is provided which comprises a phase lock loop circuit 12 which generates a reference voltage V.sub.m. The phase lock loop circuit 12 comprises first and second divider circuits 14 and 18 coupled to the input of a phase comparator 16. The output of the phase comparator 16 is coupled to a loop filter 20 which generates a DC representation of the phase differential of the inputs of the phase comparator 16. The output of the loop filter 20 is input into a bias generator 26. The output of the bias generator 26 is coupled to the input of a voltage controlled oscillator 28 which has its output coupled to the input of second divider circuit 18. The reference voltage signal V.sub.m is taken from the output of the bias generator 26 and is transmitted to remote timing elements 32, 34 and 36 where it may be used to create reference timing signals which will accurately track the reference clock signal input into phase lock loop circuit 12.