Patents by Inventor Khoi Anh Phan

Khoi Anh Phan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170125241
    Abstract: Methods of single precursor deposition of hardmask and ARC layers, are described. The resultant film is a SiOC layer with higher carbon content terminated with high density silicon oxide SiO2 layer with low carbon content. The method can include delivering a first deposition precursor to a substrate, the first deposition precursor comprising an SiOC precursor and a first flow rate of an oxygen containing gas; activating the deposition species using a plasma, whereby a SiOC containing layer over an exposed surface of the substrate is deposited. Then delivering a second precursor gas to the SiOC containing layer, the second deposition gas comprising different or same SiOC precursor with a second flow rate and a second flow rate of the oxygen containing gas and activating the deposition gas using a plasma, the second deposition gas forming a SiO2 containing layer over the hardmask, the SiO2 containing layer having very low carbon.
    Type: Application
    Filed: March 18, 2016
    Publication date: May 4, 2017
    Inventors: Shaunak MUKHERJEE, Kang Sub YIM, Deenesh PADHI, Kevin M. CHO, Khoi Anh PHAN, Chien-An CHEN, Priyanka DASH
  • Patent number: 6063531
    Abstract: A focus monitor structure is placed on a reticle or mask near the production device structures, such as integrated circuits, to monitor the focal conditions of the lithography process as well as other parameters, such as the critical dimension, and proximity effects. The focus monitor structure includes a series of densely packed parallel lines and an isolated line along with a line that is positioned orthogonally to the densely packed lines forming an "L" shaped structure. The focus monitor structure also includes a plurality of rectangular islands that create post structures when patterned in the resist layer. The lines of the focus monitor structure are approximately the critical dimension and the rectangular islands vary in width between .+-.10% of the critical dimension.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: May 16, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bhanwar Singh, Bharath Rangarajan, Khoi Anh Phan, Carmen L. Morales
  • Patent number: 5886909
    Abstract: Defects in integrated circuit wafers (10) are often difficult to diagnose, because patterned wafer inspections can only be done after certain wafer processing steps. Defect simulation is used to understand the relation between defects in the wafer (10) and the resulting wafer profiles. Defects such as particles (50) and bubbles (22) in the photoresist (28), for example, translate into a wide variety of defective profiles. Knowledge of the relation between defects and the defect profiles can assist in yield improvement efforts, since defects may be diagnosed by comparing simulated and observed defect profiles. From the simulated defect profiles, methods can be adapted to fix or correct observed defects.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: March 23, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Linda Milor, Yeng-Kaung Peng, Khoi Anh Phan, David Steele