Abstract: Embodiments disclosed herein relate to a substrate processing chamber component assembly with plasma resistant seal. In one embodiment, the semiconductor processing chamber component assembly includes a first semiconductor processing chamber component, a second semiconductor processing component, and a sealing member. The sealing member has a body formed substantially from polytetrafluoroethylene (PTFE). The sealing member provides a seal between the first and second semiconductor processing chamber components. The body includes a first surface, a second surface, a first sealing surface, and a second sealing surface. The first surface is configured for exposure to a plasma processing region. The second surface is opposite the first surface. The first sealing surface and the second sealing surface extend between the first surface and the second surface. The first sealing surface contacts the first semiconductor processing chamber component.

Abstract: Embodiments disclosed herein relate to a substrate processing chamber component assembly with plasma resistant seal. In one embodiment, the semiconductor processing chamber component assembly includes a first semiconductor processing chamber component, a second semiconductor processing component, and a sealing member. The sealing member has a body formed substantially from polytetrafluoroethylene (PTFE). The sealing member provides a seal between the first and second semiconductor processing chamber components. The body includes a first surface, a second surface, a first sealing surface, and a second sealing surface. The first surface is configured for exposure to a plasma processing region. The second surface is opposite the first surface. The first sealing surface and the second sealing surface extend between the first surface and the second surface. The first sealing surface contacts the first semiconductor processing chamber component.

Abstract: Embodiments of the invention provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in magnetoresistive random access memory applications. In one embodiment, a method of forming a MTJ structure on a substrate includes providing a substrate having a insulating tunneling layer disposed between a first and a second ferromagnetic layer disposed on the substrate, wherein the first ferromagnetic layer is disposed on the substrate followed by the insulating tunneling layer and the second ferromagnetic layer sequentially, supplying an ion implantation gas mixture to implant ions into the first ferromagnetic layer exposed by openings defined by the second ferromagnetic layer, and etching the implanted first ferromagnetic layer.

Abstract: Methods of removing photoresists from low-k dielectric films are described. For example, a method includes forming and patterning a photoresist layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Trenches are formed in the exposed portions of the low-k dielectric layer. A plurality of process cycles is performed to remove the photoresist layer. Each process cycle includes forming a silicon source layer on surfaces of the trenches of the low-k dielectric layer, and exposing the photoresist layer to an oxygen source to form an Si—O-containing layer on the surfaces of the trenches of the low-k dielectric layer and to remove at least a portion of the photoresist layer.

Abstract: Methods of forming material junctions for magnetic memory devices are described. The methods involve providing a material stack including a bottom magnetic tunneling junction layer, a tunneling barrier layer, and a top magnetic tunneling junction layer (from bottom to top) on a substrate. The top magnetic tunneling junction layer is patterned to form a top magnetic tunneling junction and then a dielectric spacer layer may be formed over the top magnetic tunneling junction. The dielectric spacer is etched to leave a vertical dielectric spacer to maintain electrical separation between the top magnetic tunneling junction and the bottom magnetic tunneling junction during and following subsequent etching/processing. In an alternative embodiment the spacer layer is lithographically defined.

Abstract: Chemical modification of non-volatile magnetic random access memory (MRAM) magnetic tunnel junctions (MTJs) for film stack etching is described. In an example, a method of etching a MTJ film stack includes modifying one or more layers of the MTJ film stack with a phosphorous trifluoride (PF3) source to provide modified regions of the MTJ film stack. The modified regions of the MTJ film stack are removed by a plasma etch process.

Abstract: Methods of patterning low-k dielectric films are described.

Abstract: Embodiments of the invention provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in magnetoresistive random access memory applications.

Abstract: Methods of patterning low-k dielectric films are described.

Abstract: Methods of removing photoresists from low-k dielectric films are described. For example, a method includes forming and patterning a photoresist layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Trenches are formed in the exposed portions of the low-k dielectric layer. A plurality of process cycles is performed to remove the photoresist layer. Each process cycle includes forming a silicon source layer on surfaces of the trenches of the low-k dielectric layer, and exposing the photoresist layer to an oxygen source to form an Si—O-containing layer on the surfaces of the trenches of the low-k dielectric layer and to remove at least a portion of the photoresist layer.

Abstract: A significantly improved low-k dielectric patterning method is described herein using plasma comprising an oxygen radical source and a silicon source to remove the photo-resist layer.

Abstract: Embodiments described herein generally relate to methods and apparatus for refurbishing a gas distribution plate assembly utilized in a deposition chamber or etch chamber. In one embodiment, a method for refurbishing a gas distribution plate assembly is provided. The method includes urging a faceplate of a gas distribution plate assembly against a polishing pad of a polishing device, the faceplate having a plurality of gas distribution holes disposed therein, providing relative motion between the faceplate and the polishing pad, and polishing the faceplate against the polishing pad.

Abstract: Methods of patterning low-k dielectric films are described.