Abstract: An integrated circuit includes a plurality of analog inputs, and an analog multiplexer (MUX). The MUX includes a common output node configured to provide a MUX output, a plurality of analog switches, and a shared buffer. Each switch includes a corresponding bootstrap circuit coupled to a control electrode of a corresponding pass transistor in which the corresponding bootstrap circuit includes a corresponding boosting capacitor. Each analog switch of the plurality of analog switches has a first input coupled to a corresponding analog input of the plurality of analog inputs, a second input, and an output coupled to the common output node. The shared buffer has an input coupled to the common output node and coupled to provide a common buffered MUX output to the second input of each of the plurality of analog switches.

Abstract: A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.

Abstract: In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.

Abstract: A receiver includes an input node coupled to receive an analog signal, a first switch coupled between the input node and a first node, a second switch coupled between the input node and a second node, a first resistive element coupled between the first node and a reference node, a second resistive element coupled between the second node and the reference node, a first capacitive element coupled to the first node, and a second capacitive element coupled to the second node. The receiver also includes a comparator having a first input coupled to the input node to receive the analog signal, and a second input coupled to the reference node to receive a reference voltage, wherein an output of the comparator controls the first and second switches.

Abstract: A voltage sampling circuit and method are provided. The voltage sampling circuit includes a capacitor having a first terminal and a second terminal. A first pre-charge circuit is coupled to a first voltage supply terminal and to the first terminal of the capacitor. The first pre-charge circuit is configured to receive a first control signal and pre-charge the capacitor to a first voltage. A switch circuit includes a first transistor having a first current electrode coupled to an input terminal of the voltage sampling circuit, a control electrode coupled to the first terminal of the capacitor, and a body electrode coupled to the second terminal of the capacitor. A second transistor having a first current electrode coupled to a second current electrode of the first transistor, a body electrode coupled to the second terminal of the capacitor, and a second current electrode coupled to an output terminal of the voltage sampling circuit.

Abstract: An analog-to-digital converter (ADC) includes a split-capacitor digital-to-analog converter (DAC) having a Most Significant Bits (MSBs) sub-DAC with one or more MSBs encoded with one or more binary capacitors and one or more MSBs encoded with one or more thermometer capacitors, a Least Significant Bits (LSBs) sub-DAC, a termination capacitor coupled to the LSBs sub-DAC, and a scaling capacitor coupled between the LSBs and MSBs sub-DACs, and coupled to receive an analog input voltage, a high reference voltage, and a low reference voltage, and to provide an output voltage.

Abstract: A thermal sensor system including at least one thermal sensor, a voltage control network, a current gain network, a current compare sensor, and a controller. The voltage control network applies reference and delta voltage levels to a thermal sensor, which develops reference and delta current signals. The current gain network is used to adjust current gain. The current compare sensor is responsive to the reference and delta current signals and provides a comparison metric. The controller selects a temperature subrange and controls the current gain network to adjust the gain of the delta current signal to determine a gain differential value indicative of the temperature. The controller may select from among different sized thermal sensors, current mode gain values, and control voltages corresponding with each of multiple temperature subranges. Any one or more of these parameters may be adjusted to adjust an operating point for selecting a corresponding temperature subrange.

Abstract: A thermal sensor system which includes a thermal sensor and a voltage control network which applies a reference voltage level and a delta voltage level to the same or different thermal sensors. The thermal sensor develops a reference current signal in response to the reference voltage level and a delta current signal in response to the delta voltage level. A current gain network adjusts gain of the delta current signal. A current compare sensor, which is responsive to the reference current signal and the delta current signal, provides a comparison metric. A controller controls the current gain network to adjust gain of the delta current signal while monitoring the comparison metric to determine a gain differential value indicative of a current ratio between the current signals. The controller determines a temperature value based on the gain differential value. A LUT may be used to retrieve the temperature.

Abstract: A thermal sensor system which includes a thermal sensor and a voltage control network which applies a reference voltage level and a delta voltage level to the same or different thermal sensors. The thermal sensor develops a reference current signal in response to the reference voltage level and a delta current signal in response to the delta voltage level. A current gain network adjusts gain of the delta current signal. A current compare sensor, which is responsive to the reference current signal and the delta current signal, provides a comparison metric. A controller controls the current gain network to adjust gain of the delta current signal while monitoring the comparison metric to determine a gain differential value indicative of a current ratio between the current signals. The controller determines a temperature value based on the gain differential value. A LUT may be used to retrieve the temperature.

Abstract: A thermal sensor system including at least one thermal sensor, a voltage control network, a current gain network, a current compare sensor, and a controller. The voltage control network applies reference and delta voltage levels to a thermal sensor, which develops reference and delta current signals. The current gain network is used to adjust current gain. The current compare sensor is responsive to the reference and delta current signals and provides a comparison metric. The controller selects a temperature subrange and controls the current gain network to adjust the gain of the delta current signal to determine a gain differential value indicative of the temperature. The controller may select from among different sized thermal sensors, current mode gain values, and control voltages corresponding with each of multiple temperature subranges. Any one or more of these parameters may be adjusted to adjust an operating point for selecting a corresponding temperature subrange.

Abstract: Apparatus are provided for a voltage-controlled oscillator module. A voltage-controlled oscillator module comprises an input node for receiving an input voltage, a voltage-controlled oscillator, and voltage translation circuitry coupled between the input node and the voltage-controlled oscillator. The voltage translation circuitry is configured to generate a control voltage based on the input voltage and the voltage-controlled oscillator generates an oscillating signal at an oscillation frequency in response to the control voltage. Biasing circuitry is coupled to the voltage translation circuitry, and the biasing circuitry is configured to adjust the ratio of the control voltage to the input voltage.

Abstract: A logic circuit including at least one evaluate circuit coupled to a static output logic circuit. In one example, the evaluate circuit includes a dynamic node, a full keeper, an evaluate device, and a logic tree. In some examples, the output logic circuit is a sampled static output logic circuit and includes a sample device. In some examples, the logic circuit includes multiple evaluate circuits, each with a dynamic node coupled to a control gate of a transistor of the output logic circuit. Some examples may include a delay in a clock signal to increase the internal race margin.

Abstract: A signal generator generates an output signal with a programmable duty cycle and includes a first buffer which generates in response to an input signal an intermediate signal having a selected edge with a voltage slope selected to vary a length of a selected phase of the output signal. A second buffer having a selected input voltage threshold generates the output signal in response to the intermediate signal.

Abstract: A signal generator generates an output signal with a programmable duty cycle and includes a first buffer which generates in response to an input signal an intermediate signal having a selected edge with a voltage slope selected to vary a length of a selected phase of the output signal. A second buffer having a selected input voltage threshold generates the output signal in response to the intermediate signal.