Patents by Inventor Khoi Phan

Khoi Phan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220127657
    Abstract: A method for detecting, in a blood or tissue sample, dormant or cell wall deficient Mycobacterium species, said method including using a Ziehl Neelsen stain as hereinbefore defined, which includes treating the sample with carbol fuchsin, followed by treating the sample with a decolouriser and with a counter stain.
    Type: Application
    Filed: February 28, 2020
    Publication date: April 28, 2022
    Inventors: John Milford AITKEN, Khoi PHAN
  • Patent number: 11313034
    Abstract: In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a hydrogen-containing gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein adjusting the flow rate of the hydrogen containing gas tunes the optical properties of the deposited amorphous silicon layer.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 26, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Weimin Zeng, Yong Cao, Daniel Lee Diehl, Huixiong Dai, Khoi Phan, Christopher Ngai, Rongjun Wang, Xianmin Tang
  • Publication number: 20190212656
    Abstract: Methods for depositing an EUV hardmask film on a substrate by physical vapor deposition which allow for reduced EUV dose. Certain embodiments relate to metal oxide hardmasks which require smaller amounts of EUV energy for processing and allow for higher throughput. A silicon or metal target can be sputtered onto a substrate in the presence of an oxygen and or doping gas containing plasma.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 11, 2019
    Inventors: Huixiong Dai, Weimin Zeng, Daniel Lee Diehl, Yong Cao, Hsiang Ning Wu, Khoi Phan, Christopher S. Ngai, Mingwei Zhu, Michael Stolfi, Nelson M. Felix, Ekmini Anuja DeSilva, Xianmin Tang
  • Publication number: 20180142343
    Abstract: In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a hydrogen-containing gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein adjusting the flow rate of the hydrogen containing gas tunes the optical properties of the deposited amorphous silicon layer.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 24, 2018
    Inventors: Weimin ZENG, Yong CAO, Daniel Lee DIEHL, Huixiong DAI, Khoi PHAN, Christopher NGAI, Rongjun WANG, Xianmin TANG
  • Publication number: 20180135183
    Abstract: Processing methods comprising depositing an initial hardmask film on a substrate by physical vapor deposition and exposing the initial hardmask film to a treatment plasma comprising a silane compound to form the hardmask.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 17, 2018
    Inventors: Weimin Zeng, Yong Cao, Daniel Lee Diehl, Khoi Phan, Huixiong Dai, Christopher S. Ngai
  • Patent number: 8028531
    Abstract: The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: October 4, 2011
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh
  • Patent number: 7709373
    Abstract: A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: May 4, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Bhanwar Singh, Khoi A Phan
  • Publication number: 20090288425
    Abstract: The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.
    Type: Application
    Filed: August 6, 2009
    Publication date: November 26, 2009
    Inventors: Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh
  • Patent number: 7604903
    Abstract: A mask is provided to be used with nanoprint lithography processes to facilitate reproduction of small features required for the production of integrated circuits. A translucent substrate is provided along with one or more three-dimensional features that include one or more vertical sidewalls. An absorbing material is deposited upon one or more of the vertical sidewalls so that light in an incident direction to an upper surface of the substrate will be absorbed by the absorbing material, resulting in light blocking features. One or more horizontal surfaces are formed upon one or more of the three-dimensional features, which allow light rays to exit a lower surface of the substrate unobstructed by the absorbing material.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: October 20, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bhanwar Singh, Srikanteswara Dakshina-Murthy, Khoi A. Phan, Bharath Rangarajan, Ramkumar Subramanian
  • Patent number: 7591902
    Abstract: The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: September 22, 2009
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bharath Rangarajan, Ramkumar Subramanian, Khoi A. Phan, Ursula Q. Quinto, Michael T. Templeton
  • Patent number: 7449348
    Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for retrograde feature profiles on an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature profile via employing a scatterometry system to detect retrograde feature profiles, and mitigating the retrograde profiles via a spacer etchback procedure.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: November 11, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Bhanwar Singh, Ramkumar Subramanian, Khoi A. Phan
  • Patent number: 7381278
    Abstract: Disclosed are immersion lithography methods involving irradiating a first photoresist through a lens and an immersion liquid, the immersion liquid contacting the lens and the first photoresist in a first apparatus; contacting the lens with a supercritical fluid in a second apparatus; and irradiating a second photoresist through the lens and an immersion liquid, the immersion liquid contacting the lens and the second photoresist in the first apparatus.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: June 3, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Bhanwar Singh, Khoi A Phan, Srikanteswara Dakshina-Murthy
  • Publication number: 20070261636
    Abstract: The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.
    Type: Application
    Filed: December 22, 2006
    Publication date: November 15, 2007
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Bharath Rangarajan, Ramkumar Subramanian, Khoi Phan, Ursula Quinto, Michael Templeton
  • Patent number: 7295288
    Abstract: Systems and methodologies are provided that account for surface variations of a wafer by adjusting grating features of an imprint lithography mask. Such adjustment employs piezoelectric elements as part of the mask, which can change dimensions (e.g., a height change) and/or move when subjected to an electric voltage. Accordingly, by regulating the amount of electric voltage applied to the piezoelectric elements a controlled expansion for such elements can be obtained, to accommodate for topography variations of the wafer surface.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: November 13, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Bhanwar Singh, Khoi A. Phan
  • Patent number: 7289193
    Abstract: Disclosed are systems and methods that employ a structural framework of cell gratings placed on a wafer surface during an immersion lithography process to restrict motion of the immersion fluid. Thus, when the stepper lens comes in contact with the immersion fluid, a typically stable immersion fluid dynamics can be maintained with the cells during the immersion lithography process. In addition, various monitoring and control systems are employed to regulate stability of the immersion fluid.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: October 30, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Bhanwar Singh, Khoi A. Phan
  • Patent number: 7262422
    Abstract: Disclosed are immersion lithography methods and systems involving irradiating a photoresist through a lens and an immersion liquid of an immersion lithography tool, the immersion liquid in an immersion space contacting the lens and the photoresist; removing the immersion liquid from the immersion space; charging the immersion space with a supercritical fluid; removing the supercritical fluid from the immersion space; and charging the immersion space with immersion liquid.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: August 28, 2007
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Bhanwar Singh, Khoi A. Phan
  • Patent number: 7251033
    Abstract: A system and method are provided for detecting contaminants or defects on a reticle in-situ. The system and method provide a system that measures the optical transmission through clear areas on a reticle and determines whether the optical transmission of a reticle has been degraded by contaminants or other defects.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: July 31, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi Phan, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian
  • Patent number: 7224456
    Abstract: A system and method for detecting bubbles in a lithographic immersion medium and for controlling a lithographic process based at least in part on the detection of bubbles is provided. A bubble monitoring component emits an incident beam that passes through the immersion medium and is incident upon a substrate to produce a reflected and/or diffracted beam(s). The reflected and/or diffracted beam(s) is received by one or more optical detectors. The presence or absence of bubbles can be derived from information extracted by scatterometry from the reflected and/or diffracted beams. A process control component interacts with a positioning component and an optical exposure component to alter a lithographic process based at least in part on the results of the scatterometry.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: May 29, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi Phan, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian
  • Patent number: 7221060
    Abstract: Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of the composite alignment mark is associated with a layer of the wafer and a second portion of the composite alignment mark is associated with a disparate layer of the wafer. An alignment component is utilized to align a reticle for a layer to be patterned to the composite alignment mark.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: May 22, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bhanwar Singh, Khoi A. Phan, Bharath Rangarajan, Iraj Emami, Ramkumar Subramanian
  • Patent number: 7187796
    Abstract: The present invention relates to monitoring and controlling a reticle fabrication process (e.g. employed with an electron beam lithography process). A typical fabrication process involves discrete stages including exposure, post-exposure bake and development. After fabrication is complete, an inspection can be performed on the reticle to determine whether any parameters during fabrication and/or any data points are outside of acceptable tolerances. The data is collected and fed into an algorithm (e.g. data-mining algorithm) utilized to determine which fabrication parameters need to be modified then sends the data to a control system (e.g. advanced process control) to facilitate needed changes to the fabrication parameters.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: March 6, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Ramkumar Subramanian, Bhanwar Singh