Patents by Inventor Khoi Phan

Khoi Phan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250062123
    Abstract: Embodiments disclosed herein include a method of thermal treatment or radical species treatment of a photoresist a metal-oxide photoresist. In an embodiment, a method of patterning a metal-oxide photoresist, such as a Sn-based photoresist, includes depositing the metal-oxide photoresist over a substrate, exposing the metal-oxide photoresist with an extreme ultra-violet (EUV) exposure to form exposed regions and non-exposed regions, developing the exposed metal-oxide photoresist, and performing a thermal treatment and/or a radical species treatment of the metal-oxide photoresist.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Inventors: SHASHANK SHARMA, KAI B. NG, NORMAN TAM, YUQI GUO, ANDY LO, HUIXIONG DAI, KHOI PHAN, CHIHAN HSU, MADHUR SACHAN, NASRIN KAZEM, ZHENXING HAN
  • Publication number: 20220127657
    Abstract: A method for detecting, in a blood or tissue sample, dormant or cell wall deficient Mycobacterium species, said method including using a Ziehl Neelsen stain as hereinbefore defined, which includes treating the sample with carbol fuchsin, followed by treating the sample with a decolouriser and with a counter stain.
    Type: Application
    Filed: February 28, 2020
    Publication date: April 28, 2022
    Inventors: John Milford AITKEN, Khoi PHAN
  • Patent number: 11313034
    Abstract: In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a hydrogen-containing gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein adjusting the flow rate of the hydrogen containing gas tunes the optical properties of the deposited amorphous silicon layer.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 26, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Weimin Zeng, Yong Cao, Daniel Lee Diehl, Huixiong Dai, Khoi Phan, Christopher Ngai, Rongjun Wang, Xianmin Tang
  • Publication number: 20190212656
    Abstract: Methods for depositing an EUV hardmask film on a substrate by physical vapor deposition which allow for reduced EUV dose. Certain embodiments relate to metal oxide hardmasks which require smaller amounts of EUV energy for processing and allow for higher throughput. A silicon or metal target can be sputtered onto a substrate in the presence of an oxygen and or doping gas containing plasma.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 11, 2019
    Inventors: Huixiong Dai, Weimin Zeng, Daniel Lee Diehl, Yong Cao, Hsiang Ning Wu, Khoi Phan, Christopher S. Ngai, Mingwei Zhu, Michael Stolfi, Nelson M. Felix, Ekmini Anuja DeSilva, Xianmin Tang
  • Publication number: 20180142343
    Abstract: In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a hydrogen-containing gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein adjusting the flow rate of the hydrogen containing gas tunes the optical properties of the deposited amorphous silicon layer.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 24, 2018
    Inventors: Weimin ZENG, Yong CAO, Daniel Lee DIEHL, Huixiong DAI, Khoi PHAN, Christopher NGAI, Rongjun WANG, Xianmin TANG
  • Publication number: 20180135183
    Abstract: Processing methods comprising depositing an initial hardmask film on a substrate by physical vapor deposition and exposing the initial hardmask film to a treatment plasma comprising a silane compound to form the hardmask.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 17, 2018
    Inventors: Weimin Zeng, Yong Cao, Daniel Lee Diehl, Khoi Phan, Huixiong Dai, Christopher S. Ngai
  • Publication number: 20070261636
    Abstract: The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.
    Type: Application
    Filed: December 22, 2006
    Publication date: November 15, 2007
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Bharath Rangarajan, Ramkumar Subramanian, Khoi Phan, Ursula Quinto, Michael Templeton
  • Patent number: 7251033
    Abstract: A system and method are provided for detecting contaminants or defects on a reticle in-situ. The system and method provide a system that measures the optical transmission through clear areas on a reticle and determines whether the optical transmission of a reticle has been degraded by contaminants or other defects.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: July 31, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi Phan, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian
  • Patent number: 7224456
    Abstract: A system and method for detecting bubbles in a lithographic immersion medium and for controlling a lithographic process based at least in part on the detection of bubbles is provided. A bubble monitoring component emits an incident beam that passes through the immersion medium and is incident upon a substrate to produce a reflected and/or diffracted beam(s). The reflected and/or diffracted beam(s) is received by one or more optical detectors. The presence or absence of bubbles can be derived from information extracted by scatterometry from the reflected and/or diffracted beams. A process control component interacts with a positioning component and an optical exposure component to alter a lithographic process based at least in part on the results of the scatterometry.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: May 29, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi Phan, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian
  • Patent number: 7173648
    Abstract: The present invention relates to visually monitoring an interior portion of a processing chamber in a semiconductor processing system. An image collector collects images of the interior of the chamber and provides an image signal indicative of a visual representation of the interior of the chamber. A viewing station receives the image signal and displays a visual representation of the interior of the chamber.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: February 6, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi Phan, Bharath Rangarajan, Bhanwar Singh, Bryan Choo
  • Publication number: 20070026345
    Abstract: Disclosed are immersion lithography methods and systems involving irradiating a photoresist through a lens and an immersion liquid of an immersion lithography tool, the immersion liquid in an immersion space contacting the lens and the photoresist; removing the immersion liquid from the immersion space; charging the immersion space with a supercritical fluid; removing the supercritical fluid from the immersion space; and charging the immersion space with immersion liquid.
    Type: Application
    Filed: July 1, 2005
    Publication date: February 1, 2007
    Inventors: Ramkumar Subramanian, Bhanwar Singh, Khoi Phan
  • Patent number: 7069155
    Abstract: The present invention generally relates to semiconductor processing, and in particular to methods and systems for analyzing photolithographic reticle defects that include detecting soft defects on a reticle and analyzing the material composition of the defects for a particular chemical signature. Specifically, the present invention scans and images a soft defect via an optical inspection scan of a reticle, mills the defect using a Focused Ion Beam, and analyzes the defect for signatures using Electron Spectroscopy for Chemical Analysis and/or Fourier Transform Infrared Spectroscopy. The present invention thus provides for real-time analysis of the chemical composition of a soft defect on a reticle without the need for a defect identification navigation system. According to an aspect of the present invention, reticle defects can be monitored without removal of a pellicle, thus facilitating increased throughput and decreased cost in reticle repair and/or cleaning.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: June 27, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi Phan, Bhanwar Singh, Bharath Rangarajan
  • Publication number: 20050193362
    Abstract: A system facilitating measurement and correction of overlay between multiple layers of a wafer is disclosed. The system comprises an overlay target that represents overlay between three or more layers of a wafer and a measurement component that determines overlay error existent in the overlay target, thereby determining overlay error between the three or more layers of the wafer. A control component can be provided to correct overlay error between adjacent and non-adjacent layers, wherein the correction is based at least in part on measurements obtained by the measurement component.
    Type: Application
    Filed: March 1, 2004
    Publication date: September 1, 2005
    Inventors: Khoi Phan, Bharath Rangarajan, Bhanwar Singh
  • Publication number: 20050048741
    Abstract: The present invention relates to inspection methods and systems utilized to provide a best means for inspection of a wafer. The methods and systems include wafer-to-reticle alignment, layer-to-layer alignment and wafer surface feature inspection. The wafer-to-reticle alignment is improved by the addition of diagonal lines to existing alignment marks to decrease the intersection size and corresponding area that a desired point can reside. Layer-to-layer alignment is improved in a similar manner by the addition of oblique and/or non-linear line segments to existing overlay targets. Also, providing for wafer surface inspection in a multitude of desired diagonal axes allows for more accurate feature measurement.
    Type: Application
    Filed: September 2, 2003
    Publication date: March 3, 2005
    Inventors: Khoi Phan, Bharath Rangarajan, Bhanwar Singh
  • Patent number: 6622547
    Abstract: A system and method for evaluating optical proximity corrected (OPC) designs is provided. The system includes an AFM measurement system for performing measurements relating to a segment of a feature pattern corresponding to a predetermined OPC mask feature. The measurement system is configured to determine a first image for the segment of the printed feature based upon the measurements. The measurement system compares the first image with another image corresponding to different OPC design to evaluate performance characteristics of the respective OPC designs.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: September 23, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi Phan, Ramkumar Subramanian, Bhanwar Singh
  • Patent number: 6573498
    Abstract: The present invention relates to a system and method for calibrating a scanning electron microscope (SEM). The method comprises measuring an electrical characteristic of a calibration standard reference sample feature and correlating the electrical measurement with an SEM measurement thereof. The correlation of the electrical and SEM measurements provides a critical dimension (CD) for the reference sample feature which can then be used to correlate SEM measurements of workpiece features. The system provides a reference sample having a measurable feature electrically connected to a probe. The probe provides an electrical measurement of the reference sample feature. The system further comprises a scanning electron microscope (SEM) adapted to provide an optical measurement of the reference sample feature. A processor is provided to correlate the optical and electrical measurements of the reference sample feature, whereby a reference feature CD is obtained.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: June 3, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bharath Rangarajan, Bhanwar Singh, Khoi Phan, Michael K. Templeton
  • Patent number: 6573497
    Abstract: The present invention relates to a system and method for calibrating a scanning electron microscope (SEM). The method comprises measuring an electrical characteristic of a calibration standard reference sample feature via a current induced by an electron beam (e-beam) and correlating the e-beam induced current measurement with an SEM measurement thereof. The correlation of the e-beam induced current and SEM measurements provides a critical dimension (CD) for the reference sample feature which can then be used to correlate SEM measurements of workpiece features. The system provides a reference sample having a measurable feature electrically connected to a probe. The probe provides an electrical measurement of the reference sample feature based on an e-beam induced current. The system further comprises a scanning electron microscope (SEM) adapted to provide an optical measurement of the reference sample feature and workpiece features.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: June 3, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bharath Rangarajan, Bhanwar Singh, Khoi Phan, Michael K. Templeton
  • Patent number: 6570157
    Abstract: The present invention relates to a system and method for calibrating a scanning electron microscope (SEM). The method comprises using a reference having multiple features of different dimensions and spatial interrelationships, wherein more than one feature dimension or spacing is measured using the SEM prior to measuring a workpiece. The dimensional and/or spatial measurements from the reference sample are correlated to obtain one or more calibration factors for the SEM. The calibration factor or factors may then be correlated with a workpiece SEM measurement to obtain a workpiece critical dimension (CD). A system is provided for calibrating a SEM including a reference with various measurable features of different dimensions and/or spacing. The system comprises an SEM to measure one or more reference sample feature dimensions and/or spacings and a processor or other device to correlate the measurement data to obtain one or more calibration factors.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: May 27, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bhanwar Singh, Khoi Phan, Bharath Rangarajan
  • Patent number: 6513151
    Abstract: A method for new product mask evaluation is provided. Focus exposure matrices are printed at one or more layers (e.g., active gate) on full flow production wafers. The focus exposure matrices are then analyzed to produce data that facilitates detecting printed defects. The full flow production wafers are also subjected to end of line electrical testing to determine bit level errors. Print defects can be correlated with bit level errors to increase confidence in detected defects. The method includes a hierarchy of testing layers, each of which produce data that can be employed in detecting defects in a reticle and/or producing a yield analysis. The method involves scanning a reticle upon which the new product mask is etched and performing a printability simulation to determine what affect, if any, detected reticle defects will have on printing defects on a wafer.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: January 28, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeff Erhardt, Khoi Phan
  • Patent number: 6510730
    Abstract: A system and method for evaluating optical proximity corrected (OPC) designs is provided. The system includes an AFM measurement system for performing measurements relating to a segment of a feature pattern corresponding to a predetermined OPC mask feature. The measurement system is configured to determine a first image for the segment of the printed feature based upon the measurements. The measurement system compares the first image with another image corresponding to different OPC design to evaluate performance characteristics of the respective OPC designs.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: January 28, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi Phan, Ramkumar Subramanian, Bhanwar Singh