Abstract: In a data processing system, a memory control unit (22) provides a control register bit field (60), logic, and a state machine (62) which facilitate a programmable number of clocks for an initial access to an on-chip memory (20). Specifically, the memory control unit (22) allows an external user to modify memory control signals to provide consistent access times across different frequencies of the system clock and allows memory control signals to be modified to optimize access time dynamically. Also, programmable control of the control signals to the memory (20) allows the memory to operate at system clock frequencies which are higher than expected.

Abstract: Clock frequency and number of stages of a charge pump for nonvolatile memories are automatically adjusted to compensate for lower efficiency due to lower power supply, higher temperature, or weaker process. A low voltage detector will cause the charge pump to increase the charge pump's clock frequency and number of stages when a low voltage is detected, making the charge pump's capability constant over a voltage range. A counter timing programming/erasing time will cause the charge pump clock frequency and number of stages to increase when the programming/erasing time exceeds certain thresholds. This boosts the charge pump's drivability for a weaker process, higher temperature, or aged cells.