Abstract: An interface device includes a first connector to connect to a port of a switch, where the switch sends data packets at a first rate and a second connector to connect to a port of a device, where the device sends data packets at a second rate slower than the first rate. A physical control layer connects to the first connector and the second connector to control a flow of data packets. The physical control layer throttles down the flow of data packets to the second connector when the data packets are travelling from the first connector to the second connector, and matches a speeds of the flow of data packets to the first connector when the data packets are travelling from the second connector to the first connector.

Abstract: The present invention relates to a system and method for implementing auto-configurable default polarity. More specifically, the present invention relates to a transceiver module comprising, for example, a single chip multi-sublayer PHY, where the single chip multi-sublayer PHY is adapted to implement auto-configurable default polarity. In one embodiment, the transceiver module comprises at least one program module adapted to be programmed with at least a default polarity setting. The single-chip multi-sublayer PHY comprises at least one selection register communicating with at least the program module, where the selection register is adapted to store at least the default polarity setting. The single chip multi-sublayer PHY further comprises at least one multiplexer communicating with at least the selection register and adapted to select one polarity from at least two possible polarities based at least in part on the default polarity setting.

Abstract: An interface device includes a first connector to connect to a port of a switch, where the switch sends data packets at a first rate and a second connector to connect to a port of a device, where the device sends data packets at a second rate slower than the first rate. A physical control layer connects to the first connector and the second connector to control a flow of data packets. The physical control layer throttles down the flow of data packets to the second connector when the data packets are travelling from the first connector to the second connector, and matches a speeds of the flow of data packets to the first connector when the data packets are travelling from the second connector to the first connector.

Abstract: The present invention relates to a system and method for implementing auto-configurable default polarity. More specifically, the present invention relates to a transceiver module comprising, for example, a single chip multi-sublayer PHY, where the single chip multi-sublayer PHY is adapted to implement auto-configurable default polarity. In one embodiment, the transceiver module comprises at least one program module adapted to be programmed with at least a default polarity setting. The single-chip multi-sublayer PHY comprises at least one selection register communicating with at least the program module, where the selection register is adapted to store at least the default polarity setting. The single chip multi-sublayer PHY further comprises at least one multiplexer communicating with at least the selection register and adapted to select one polarity from at least two possible polarities based at least in part on the default polarity setting.

Abstract: The present invention relates to a system and method for implementing auto-configurable default polarity. More specifically, the present invention relates to a transceiver module comprising, for example, a single chip multi-sublayer PHY, where the single chip multi-sublayer PHY is adapted to implement auto-configurable default polarity. In one embodiment, the transceiver module comprises at least one program module adapted to be programmed with at least a default polarity setting. The single-chip multi-sublayer PHY comprises at least one selection register communicating with at least the program module, where the selection register is adapted to store at least the default polarity setting. The single chip multi-sublayer PHY further comprises at least one multiplexer communicating with at least the selection register and adapted to select one polarity from at least two possible polarities based at least in part on the default polarity setting.

Abstract: Methods and systems for automatic CAT cable configuration are disclosed and may comprise configuring a single network interface to handle processing of signals communicated over differently coupled CAT cable configurations. One or more switching devices, which may comprise multiplexers or configurable switches, may be electronically or manually configured to couple a single network interface to one or more corresponding conductors associated with the CAT cable configurations. The configuration may enable at least a portion of the one or more switching devices and disable other portions of the switching devices. The single network interface may handle processing of data rates ranging from 1 BaseT to multi-gigabit speeds. The CAT cable configurations may comprise: CAT 3, CAT 4, CAT 5, CAT 5E, CAT 6, CAT 6A, CAT 7 and CAT 7A.

Abstract: The present invention relates to a register for a single chip multi-sublayer PHY. More specifically, the present invention relates to a transceiver module including a single chip multi-layer PHY having one or more shadow registers. The transceiver module includes one or more storage modules adapted to store transceiver module local data. The shadow registers are adapted to facilitate collection of the local data from the storage modules and communicate the collected data to another portion of the transceiver module and/or to the upper lever system using at least one interface communicating with the shadow register.

Abstract: The present invention relates to a register for a single chip multi-sublayer PHY. More specifically, the present invention relates to a transceiver module including a single chip multi-layer PHY having one or more shadow registers. The transceiver module includes one or more storage modules adapted to store transceiver module local data. The shadow registers are adapted to facilitate collection of the local data from the storage modules and communicate the collected data to another portion of the transceiver module and/or to the upper lever system using at least one interface communicating with the shadow register.

Abstract: An on-the-fly integrity checking system which dupicates data passing through a main systems bus, functions concurrently to recognize the size of data blocks being transferred from a sending module to a receiving module. Each word transferred is immediately parity checked. A counter indicates when the entire data block has transferred so as to initiate the comparison of an original block EDC signature with that of a internally generated EDC value to indicate the validity or invalidity of the data transfer. No delay is involved on the data transfer operations of the main system bus due to the integrity checking system operating independently as an independent module which does not delay data transfers on the main system bus.

Abstract: Multiple numbers of "sets" of sender-receiver units operate concurrently to transfer blocks of data. The number of blocks to be transferred in each set is predetermined by a main host computer which registers the number-of-blocks-to-be-transferred into a protocol-controller in each set of sender-receiver units. An associated data feeder control system monitors the number of data blocks residing in a buffer memory, which has dedicated storage for each sender-receiver unit, and will only permit data block transfer to receiver units only to the amount presently available in the buffer memory until, eventually, the predetermined number of data blocks, for each set, is transferred to completion.

Abstract: A buffer memory holding blocks of data received from a main host computer has dedicated portions for data destined for different sets of sender-receiver units. Each sender-receiver unit has a channel bus path to the buffer memory and each channel bus is monitored by an on-the-fly integrity checking circuit.A control processor and associated bus arbitration logic provide signals to a multiplexer so as to allocate equal access periods to each channel bus for connection to the buffer memory. A data feeder control on each transfer channel senses the availability of data block words in each dedicated segment of the buffer memory so that partial transfers of word blocks may occur on minor cycles with subsequent completion of the blocks of data words on a major transfer cycle.

Abstract: A device interface module provides multiple concurrently operating data transfer channels between multiple groups of peripheral devices and ad multiported buffer memory which communicates via an interface bus to other external modules of a computer system.

Abstract: A mass storage/retrieval module for controlling the storage and retrieval operations of massive amounts of data in peripheral devices such as tape, disk, optical, etc. provides for a buffer memory system in each of the interface control modules which permit simultaneous and concurrent writing to buffer storage and reading out of buffer storage through multiple ports for high rates of data transfer operations. Redundancy and high reliability is provided in that each module of the system has dual busses and live replacement units such that, upon failure, an alternate unit can carry the circuitry requirements until the failing unit has been replaced.

Abstract: A mass storage/retrieval module for controlling the storage and retrieval operations of massive amounts of data in peripheral devices such as tape, disk, optical, etc. provides for a buffer memory system in each of the interface control modules which permit simultaneous and concurrent writing to buffer storage and reading out of buffer storage through multiple ports for high rates of data transfer operations. Redundancy and high reliability is provided in that each module of the system has dual busses and live replacement units such that, upon failure, an alternate unit can carry the circuitry requirements until the failing unit has been replaced.