Abstract: A system and method for mapping Intellectual Property (IP) components onto a pre-fabricated chip slice allows a user to select a target location for placement of an IP component onto a slice. A slice definition of the pre-fabricated chip slice is searched for a legal location for the IP component that is near to the target location. The IP component is mapped to the legal location.

Abstract: A system and method for mapping IP components onto a pre-fabricated chip slice allows a user to select a target location for placement of an IP component onto a slice. A slice definition of the pre-fabricated chip slice is searched for a legal location for the IP component that is near to the target location. The IP component is mapped to the legal location.

Abstract: A command processor of an integrated circuit design suite has a graphical user interface and a command interpreter for interpreting user commands. The graphical user interface is specified entirely by a user at run time. One or more design tools corresponding to processes within an integrated circuit design process operate under the control of the command processor and within the graphical user interface.

Abstract: A method is provided for fabricating an integrated circuit having a logical function. The method includes fabricating first and second routing layer masks and a first via mask. The first routing layer mask includes power supply segments and signal segments. The second routing layer mask includes signal segments and filler segments, wherein the filler segments are located in unused areas of the second routing layer mask. The first via mask defines vias that electrically couple the filler segments to the power supply segments. If the logical function is changed after the masks have been fabricated, a second via mask is fabricated. The second via mask decouples a filler segment from the power supply segments and couples the filler segment to a signal segment defined by the first routing layer mask to implement the logical function change. The integrated circuit is then fabricated with the first and second routing layer masks and the second via mask.

Abstract: A method is provided for fabricating an integrated circuit having a logical function. The method includes fabricating first and second routing layer masks and a first via mask. The first routing layer mask includes power supply segments and signal segments. The second routing layer mask includes signal segments and filler segments, wherein the filler segments are located in unused areas of the second routing layer mask. The first via mask defines vias that electrically couple the filler segments to the power supply segments. If the logical function is changed after the masks have been fabricated, a second via mask is fabricated. The second via mask decouples a filler segment from the power supply segments and couples the filler segment to a signal segment defined by the first routing layer mask to implement the logical function change. The integrated circuit is then fabricated with the first and second routing layer masks and the second via mask.