Patents by Inventor Khosrow Hedayati

Khosrow Hedayati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital multiplier architecture with triple array summation of partial products
    Patent number: 4831577
    Abstract: The invention performs the multiplication and/or accumulation of digital numbers in either two's complement of unsigned magnitude representation. A modified Booth algorithm minimizes the number of partial products generated. Two adder arrays sum the partial products in parallel to generate intermediate values which are then summed by a third adder array. The partial products are divided between the two adder arrays in a manner which optimizes the speed of the circuit.
    Type: Grant
    Filed: September 17, 1986
    Date of Patent: May 16, 1989
    Assignee: Intersil, Inc.
    Inventors: James Y. Wei, Khosrow Hedayati
  • Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate
    Patent number: 4749886
    Abstract: A parallel EXCLUSIVE or and EXCLUSIVE NOR gate comprising four tri-inverter circuits in which the input transistors of the tri-inverter circuits are shared.
    Type: Grant
    Filed: October 9, 1986
    Date of Patent: June 7, 1988
    Assignee: Intersil, Inc.
    Inventor: Khosrow Hedayati