Patents by Inventor Khun Ban

Khun Ban has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10452443
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Keqiang Wu, Kingsum Chow, Ying Feng, Khun Ban
  • Patent number: 10120731
    Abstract: Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: November 6, 2018
    Assignee: INTEL CORPORATION
    Inventors: Khun Ban, Kingsum Chow, Shirish Aundhe, Sandhya Viswanathan
  • Publication number: 20180241811
    Abstract: Disclosed is a mechanism for determining incompatible co-tenants in a cloud network. Cloud performance data is received indicating resource usage of tenants operating on a per server basis. Cross-correlation analysis is performed on past resource usage for each tenant pair operating on the server to determine correlated tenant pairs. Time series forecasting of predicted resource usage is performed for each tenant in the correlated tenant pairs. Cross-correlation analysis is then performed on the predicted resource usage for each correlated tenant pair to determine incompatible co-tenant pairs. The determined incompatible co-tenant pairs may be forwarded toward an orchestration system for hardware resource allocation in the cloud network.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 23, 2018
    Applicant: Intel Corporation
    Inventors: Li Chen, Krishnaswamy Viswanathan, Khun Ban
  • Patent number: 9954744
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for estimation of application execution performance variations on a processor, without a priori knowledge of the application. A system may include network traffic data collection circuitry configured to sample a first network traffic statistic, from a network interface circuit associated with the processor, at a first sampling time interval during the application execution. The network traffic data collection circuitry may also be configured to sample a second network traffic statistic from the network interface circuit at a second sampling time interval during the application execution.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: April 24, 2018
    Assignee: INTEL CORPORATION
    Inventors: Keqiang Wu, Kingsum Chow, Ying Feng, Khun Ban, Zhidong Yu
  • Publication number: 20170337083
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.
    Type: Application
    Filed: August 7, 2017
    Publication date: November 23, 2017
    Applicant: Intel Corporation
    Inventors: KEQIANG WU, KINGSUM CHOW, YING FENG, KHUN BAN
  • Patent number: 9760404
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Keqiang Wu, Kingsum Chow, Ying C. Feng, Khun Ban
  • Publication number: 20170060635
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.
    Type: Application
    Filed: September 1, 2015
    Publication date: March 2, 2017
    Applicant: INTEL CORPORATION
    Inventors: KEQIANG WU, KINGSUM CHOW, YING C. FENG, KHUN BAN
  • Publication number: 20170063652
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for estimation of application execution performance variations on a processor, without a priori knowledge of the application. A system may include network traffic data collection circuitry configured to sample a first network traffic statistic, from a network interface circuit associated with the processor, at a first sampling time interval during the application execution. The network traffic data collection circuitry may also be configured to sample a second network traffic statistic from the network interface circuit at a second sampling time interval during the application execution.
    Type: Application
    Filed: September 1, 2015
    Publication date: March 2, 2017
    Applicant: INTEL CORPORATION
    Inventors: KEQIANG WU, KINGSUM CHOW, YING FENG, KHUN BAN, ZHIDONG YU
  • Patent number: 9286224
    Abstract: In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: March 15, 2016
    Assignee: Intel Corporation
    Inventors: Seth H. Pugsley, Robert L. Scott, Zeshan A. Chishti, Peng-Fei Chuang, Khun Ban, Christopher B. Wilkerson, Shih-Lien L. Lu, Kingsum Chow
  • Publication number: 20150220372
    Abstract: Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.
    Type: Application
    Filed: July 15, 2013
    Publication date: August 6, 2015
    Inventors: Khun Ban, Kingsum Chow, Shirish Aundhe, Sandhya Viswanathan
  • Publication number: 20150149714
    Abstract: In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Inventors: Seth H. Pugsley, Robert L. Scott, Zeshan A. Chishti, Peng-Fei Chuang, Khun Ban, Christopher B. Wilkerson, Shih-Lien L. Lu, Kingsum Chow