Abstract: In one implementation, an analytical approach to determining an improved and/or optimal design of a matching network in a capacitive or inductive WPT system is provided. In one implementation, for example, a framework is provided to enable stage(s) of the network to simultaneously provide gain and compensation. The multistage matching network efficiency can be improved and/or optimized, such as by using the method of Lagrange multipliers, resulting in the optimum distribution of gain and compensation among the L-section stages.

Abstract: A systematic procedure for the synthesis of hybrid feedforward control architectures for pulse-width modulated (PWM) switching converters is provided. In this hybrid feedforward control architecture selected converter variables are sensed and utilized in a particular way based on the converter open-loop characteristics to determine the duty-cycle needed to achieve a control objective. Compared to standard feedback control techniques, advantages can include simpler controller implementation, more convenient sensing, and improved static and dynamic regulation. An example systematic procedure for developing hybrid feedforward controllers is illustrated by first considering a previously known example of hybrid feedforward control: hybrid feedforward control of a boost power factor correction (PFC) rectifier operating in discontinuous conduction mode (DCM).

Abstract: Multistage matching networks and analytical frameworks for improving and/or optimizingthe networks is provided. In one example, a framework relaxes the resistive constraint on the input and load impedances of the stages of a multistage matching network and allows them to be complex. Based on this framework, the design of multistage matching networks can be improved or optimized, such as using a method of Lagrange multipliers. A design optimization approach, for example, can be used to predict an optimum distribution of gains and impedance characteristics among the stages of a multistage matching network. The efficiency of matching networks designed using this example approach is compared with a conventional design approach, and it is shown that significant efficiency improvements are possible.

Abstract: A power converter for converting DC power to DC power includes an inverter stage having two or more switched inverters configured to receive DC power from a source and produce a switched AC output power signal. A transformation stage is coupled to receive the switched output power signal from the inverter stage, shape the output power signal, and produce a shaped power signal. A rectifier stage having two or more switched inverters coupled to receive the shaped power signal and convert the shaped power signal to a DC output power signal is included. A controller circuit is coupled to operate the power converter in a variable frequency multiplier mode where at least one of the switched inverters is switched at a frequency or duty cycle that results in an output signal having a frequency that is a harmonic of the fundamental frequency being generated by the power converter.

Abstract: A split drive transformer (SDT) and use of such a transformer in a power converter is described. The power converter includes a power and distributor circuit configured to receive one or more input signals and provides multiple signals to a first side of the SDT. The SDT receives the signals provided to the first side thereof and provides signals at a second side thereof to a power combiner and rectifier circuit which is configured to provide output signals to a load. In some embodiments, the SDT may be provided as a switched-capacitor (SC) SDT. In some embodiments, the power converter may optionally include a level selection circuit (LSC) on one or both of the distributor and combiner sides.

Abstract: A power converter for converting DC power to DC power includes an inverter stage having two or more switched inverters configured to receive DC power from a source and produce a switched AC output power signal. A transformation stage is coupled to receive the switched output power signal from the inverter stage, shape the output power signal, and produce a shaped power signal. A rectifier stage having two or more switched inverters coupled to receive the shaped power signal and convert the shaped power signal to a DC output power signal is included. A controller circuit is coupled to operate the power converter in a variable frequency multiplier mode where at least one of the switched inverters is switched at a frequency or duty cycle that results in an output signal having a frequency that is a harmonic of the fundamental frequency being generated by the power converter.

Abstract: A stacked switched capacitor (SSC) energy buffer circuit includes a switching network and a plurality of energy storage capacitors. The switching network need operate at only a relatively low switching frequency and can take advantage of soft charging of the energy storage capacitors to reduce loss. Thus, efficiency of the SSC energy buffer circuit can be extremely high compared with the efficiency of other energy buffer circuits. Since circuits utilizing the SSC energy buffer architecture need not utilize electrolytic capacitors, circuits utilizing the SSC energy buffer architecture overcome limitations of energy buffers utilizing electrolytic capacitors. Circuits utilizing the SSC energy buffer architecture (without electrolytic capacitors) can achieve an effective energy density characteristic comparable to energy buffers utilizing electrolytic capacitors.

Abstract: A power converter for converting DC power to DC power includes an inverter stage having two or more switched inverters configured to receive DC power from a source and produce a switched AC output power signal. A transformation stage is coupled to receive the switched output power signal from the inverter stage, shape the output power signal, and produce a shaped power signal. A rectifier stage having two or more switched inverters coupled to receive the shaped power signal and convert the shaped power signal to a DC output power signal is included. A controller circuit is coupled to operate the power converter in a variable frequency multiplier mode where at least one of the switched inverters is switched at a frequency or duty cycle that results in an output signal having a frequency that is a harmonic of the fundamental frequency being generated by the power converter.

Abstract: Described is a method and apparatus for per-panel photovoltaic energy extraction with integrated converters. Also described are switched-capacitor (SC) converters have been evaluated for many applications because of the possibility for on-chip integration; applications to solar arrays are no exception. Also described is a comprehensive system-level look at solar installations, finding possibilities for optimization at and between all levels of operation in an array. Specifically, novel concepts include new arrangements and options for applying switched-capacitor circuits at 3 levels: for the panel and sub-panel level, as part of the overall control strategy, and for ensuring stable and robust interface to the grid with the possibility of eliminating or reducing the use of electrolytic capacitors.

Abstract: A split drive transformer (SDT) and use of such a transformer in a power converter is described. The power converter includes a power and distributor circuit configured to receive one or more input signals and provides multiple signals to a first side of the SDT. The SDT receives the signals provided to the first side thereof and provides signals at a second side thereof to a power combiner and rectifier circuit which is configured to provide output signals to a load. In some embodiments, the SDT may be provided as a switched-capacitor (SC) SDT. In some embodiments, the power converter may optionally include a level selection circuit (LSC) on one or both of the distributor and combiner sides.

Abstract: Described herein is a stacked switched capacitor (SSC) energy buffer circuit architecture and related design and control techniques.

Abstract: SSC energy buffer circuit includes a switching network and a plurality of energy storage capacitors. The switching network may operate at a relatively low switching frequency and can take advantage of soft charging of the energy storage capacitors to reduce loss. Efficiency of the SSC energy buffer circuit can be extremely high compared with the efficiency of other energy buffer circuits. The SSC energy buffer architecture exhibits losses that scale with the amount of energy buffered, such that a relatively high efficiency can be achieved across a desired operating range. Improvements in SSC energy buffer circuits include, in various implementations, the use of ground reference gate drive, the elimination of a separate precharge circuit through control of at least a portion of the switches of the SSC energy buffer circuit, and/or optimized ratio of capacitance values of two or more capacitors in an SSC energy buffer circuit.

Abstract: A circuit includes a reconfigurable rectifier, a voltage balancer, and a pair of converters. The reconfigurable rectifier includes an ac input port and three output ports. In a first configuration, the reconfigurable rectifier can deliver power at a first output port and, in a second configuration, to at least a second output port. The voltage balancer includes first and second ports coupled to second and third output ports of the reconfigurable rectifier and is configured to balance received voltage at the first and second ports. The first converter has an input coupled to the first port of the voltage balancer and an output at which a first converted voltage signal is provided. The second converter has an input coupled to the second port of the voltage balancer and an output at which a second converted voltage signal is provided.

Abstract: A power converter for converting DC power to DC power includes an inverter stage having two or more switched inverters configured to receive DC power from a source and produce a switched AC output power signal. A transformation stage is coupled to receive the switched output power signal from the inverter stage, shape the output power signal, and produce a shaped power signal. A rectifier stage having two or more switched inverters coupled to receive the shaped power signal and convert the shaped power signal to a DC output power signal is included. A controller circuit is coupled to operate the power converter in a variable frequency multiplier mode where at least one of the switched inverters is switched at a frequency or duty cycle that results in an output signal having a frequency that is a harmonic of the fundamental frequency being generated by the power converter.

Abstract: An impedance control resonant power converter (converter) operated at a fixed switching frequency includes an impedance control network (ICN) coupled between two or more inverters operated at a fixed duty ratio with a phase shift between them and one or more rectifiers. The phase shift is used to control output power or compensate for variations in input or output voltage. The converter operates at fixed frequency yet achieves simultaneous zero voltage switching (ZVS) and zero or near zero current switching (ZCS) across a wide operating range. Output power may be controlled by: (1) changing phase shift between inverters; or (2) adjusting phase shift between inverters depending upon input and/or output voltages so that an admittance presented to the inverters is conductive and then turning the converter on and off at a frequency lower than the converter switching frequency to control output power below a value set by the phase shift.

Abstract: A stacked switched capacitor (SSC) energy buffer circuit includes a switching network and a plurality of energy storage capacitors. The switching network need operate at only a relatively low switching frequency and can take advantage of soft charging of the energy storage capacitors to reduce loss. Thus, efficiency of the SSC energy buffer circuit can be extremely high compared with the efficiency of other energy buffer circuits. Since circuits utilizing the SSC energy buffer architecture need not utilize electrolytic capacitors, circuits utilizing the SSC energy buffer architecture overcome limitations of energy buffers utilizing electrolytic capacitors. Circuits utilizing the SSC energy buffer architecture (without electrolytic capacitors) can achieve an effective energy density characteristic comparable to energy buffers utilizing electrolytic capacitors.

Abstract: A stacked switched capacitor (SSC) energy buffer circuit includes a switching network and a plurality of energy storage capacitors. The switching network need operate at only a relatively low switching frequency and can take advantage of soft charging of the energy storage capacitors to reduce loss. Thus, efficiency of the SSC energy buffer circuit can be extremely high compared with the efficiency of other energy buffer circuits. Since circuits utilizing the SSC energy buffer architecture need not utilize electrolytic capacitors, circuits utilizing the SSC energy buffer architecture overcome limitations of energy buffers utilizing electrolytic capacitors. Circuits utilizing the SSC energy buffer architecture (without electrolytic capacitors) can achieve an effective energy density characteristic comparable to energy buffers utilizing electrolytic capacitors.

Abstract: Described herein is a stacked switched capacitor (SSC) energy buffer circuit architecture and related design and control techniques.

Abstract: Described is a method and apparatus for per-panel photovoltaic energy extraction with integrated converters. Also described are switched-capacitor (SC) converters have been evaluated for many applications because of the possibility for on-chip integration; applications to solar arrays are no exception. Also described is a comprehensive system-level look at solar installations, finding possibilities for optimization at and between all levels of operation in an array. Specifically, novel concepts include new arrangements and options for applying switched-capacitor circuits at 3 levels: for the panel and sub-panel level, as part of the overall control strategy, and for ensuring stable and robust interface to the grid with the possibility of eliminating or reducing the use of electrolytic capacitors.