Abstract: Methods and apparatus to perform noise cancellation in radios are described. According to one example, a receiver includes a front end amplifier to receive and amplify an input signal; a downconverter to downconvert the amplified input signal; a feedback estimator to estimate a noise in the downconverted signal; and a feedback implementer to produce a feedback signal based on the estimated noise and to couple the feedback signal to the front end amplifier.

Abstract: A system and method for time aligning signals in transmitters. A transmitter includes a first signal path coupled to a first data input, a second signal path coupled to a second data input, an error signal energy source coupled to the first and second signal paths, the error signal energy source generates an error signal responsive to a time alignment difference between a first data stream and a second data stream, a time alignment circuit coupled to the error signal energy source, to the first and second data inputs, the time alignment circuit generates a digital control word responsive to the error signal, to the first and second data streams, and a timing adjust unit coupled to the time alignment circuit, to the first and second signal paths, the timing adjust unit inserts a delay proportional to the digital control word in either signal paths.

Abstract: A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.

Abstract: One embodiment of the invention includes a mixed-signal filter. The mixed-signal filter comprises an analog signal path configured to process a first analog signal and an analog-to-digital converter (ADC) configured to convert the processed first analog signal to a digital signal. The mixed-signal filter also comprises a programmable digital feedback filter configured to filter the digital signal and a digital-to-analog converter (DAC) configured to convert the filtered digital signal to a second analog signal. The mixed-signal filter further comprises a signal combiner configured to combine an analog input signal of the mixed-signal filter and the second analog signal to generate the first analog signal.

Abstract: System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

Abstract: Methods and apparatus to provide an auxiliary receive path to support transmitter functions are disclosed. An example transceiver includes an antenna and a duplexer coupled to the antenna. A transmitter is coupled to the duplexer to output a transmit signal at a transmit frequency. A receiver is coupled to the duplexer to receive a received signal at a receiver frequency. A signal processor is coupled to the transmitter and receiver. An auxiliary receiver is communicatively coupled to the signal processor to receive the transmit signal output from the transmitter and send an auxiliary receiver signal to the signal processor. The signal processor adjusts the transmit signal based on the auxiliary receiver signal.

Abstract: A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional cycles of the first voltage waveform are obtained. The samples are obtained in response to a control signal indicative of a code used to produce the first voltage waveform, and the samples are combined to produce the second voltage waveform.

Abstract: In one embodiment, a WCDMA FDD system includes an embedded filter that provides a complex load to transistors in a low noise amplifier. The complex load can be constructed using passive and/or active devices and creates an arbitrary transfer function that supports selective Q-enhancement of poles or zeros. One particular implementation of the embedded filter is in the form of an LC tank circuit. The LC tank circuit is operably coupled to the output of the low noise amplifier and creates a transfer function whose poles and zeros can be selected to reject transmitter leakage in the WCDMA system, while maintain a desirable gain at the frequency of operation.

Abstract: Methods and systems to provide digitally controlled crystal oscillators are disclosed. One example method includes determining a state of an oscillator system and selecting a first output of a digitally controlled crystal oscillator or a second output of a second oscillator based on the determination. In an example implementation, the second oscillator is a ring oscillator.

Abstract: The present invention provides a spurious tone suppressor for use with a power supply system. In one embodiment, the spurious tone suppressor includes an error signal generator configured to provide a spur error signal proportional to a spur signal associated with the power supply system. Additionally, the spurious tone suppressor also includes an adaptive spur cancellation engine coupled to the error signal generator and configured to adaptively process the spur error signal and generate a corresponding anti-spur signal that is injected into the power supply system to suppress the spur signal.

Abstract: System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer predictor 840) coupled to a digital output of a direct RF radio receiver (for example, radio receiver 800). The interferer predictor predicts the presence of interferers and feeds the information back to a sampling unit (for example, sampling unit 805) through a feedback circuit (for example, feedback unit 845) through the use of charge sharing. The interferers are then eliminated in the sampling unit. Additionally, the number and placement of zeroes in a filter in the sampling unit is increased and changed through the implementation of arbitrary-coefficient finite impulse response filters.

Abstract: The present invention provides an offset balancer for use with a differential mixer employing a wireless reception and an offset quantifier configured to indicate an existing DC offset of the mixer corresponding to an existing second-order intercept point applicable to the wireless reception. In one embodiment, the offset balancer includes an offset adjuster coupled to the offset quantifier and configured to provide an offset adjustment to the existing DC offset based on increasing the existing second-order intercept point.

Abstract: The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.

Abstract: In a method and system for performing automatic gain control (AGC) in a receiver, an automatic integrated controller (AICTR) device includes a gain controller (GC) to control an amplitude of an input signal provided to the receiver, with the interfering signal and the signal of interest being included in the input signal. The GC maintains the amplitude within a predefined range to operate the receiver substantially close to saturation. The AICTR device also includes a frequency controller (FC) to control a frequency of a local oscillator (LO) signal. The LO signal is mixed with the input signal to generate an intermediate frequency (IF) signal. The FC changes the frequency of the LO signal to increase or decrease a frequency of the IF signal. A greater attenuation is provided to the interfering signal compared to an attenuation for the signal of interest by the reduction in frequency of the IF signal.

Abstract: Methods and apparatus to compensate for I/Q mismatch in quadrature receivers are disclosed. An example apparatus disclosed herein comprises a correction engine using first filter coefficients to compensate for I/Q mismatch present in a received quadrature signal; an adaptation engine to adapt second filter coefficients based on I/Q mismatch present in the received quadrature signal; and coefficient controller to occasionally adjust the first filter coefficients based on the second filter coefficients.

Abstract: System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

Abstract: System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

Abstract: When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

Abstract: Methods, apparatus, and articles of manufacture are disclosed for removing an undesired component from a low intermediate frequency signal having an intermediate center frequency and an undesired component at a first frequency. One example method may include determining an amplitude of the undesired component; frequency shifting the low intermediate frequency signal from the intermediate center frequency to produce a zero intermediate frequency signal; filtering the zero intermediate frequency signal; generating a tone based on the amplitude of the undesired component; and subtracting the tone from the filtered zero intermediate frequency signal to remove the undesired component.

Abstract: A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.