Patents by Inventor Khushrav S. Chhor
Khushrav S. Chhor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7806324Abstract: By decreasing the amount of card substrate required in a memory card to support the actual memory unit, the test interface of the card, which is usually removed before final assembly of the card, can be brought within the allowable length of the finished card and can, therefore, remain on the card permanently. Consequently, in the event of a field failure, the test interface remains available for testing the card and diagnosing the location and cause of the failure.Type: GrantFiled: January 24, 2008Date of Patent: October 5, 2010Assignee: SanDisk 3D, LLCInventors: Khushrav S. Chhor, Tae-Hee Lee
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Patent number: 7432599Abstract: A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may include the capability to utilize bonding pads on all four sides of an integrated circuit. A lead frame structure may be divided into first and second portions. The first portion may be adapted to receive the stacked integrated circuits and the second portion may include a plurality of conductors. The first portion may also be adapted to couple at least one of the integrated circuits to power and ground conductors on the second portion. In one embodiment, the first portion may include the lead frame paddle and a conductive ring. In another embodiment, the first portion may include first and second coplanar elements.Type: GrantFiled: January 5, 2006Date of Patent: October 7, 2008Assignee: SanDisk 3D LLCInventors: Vani Verma, Khushrav S. Chhor
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Patent number: 7352199Abstract: By decreasing the amount of card substrate required in a memory card to support the actual memory unit, the test interface of the card, which is usually removed before final assembly of the card, can be brought within the allowable length of the finished card and can, therefore, remain on the card permanently. Consequently, in the event of a field failure, the test interface remains available for testing the card and diagnosing the location and cause of the failure.Type: GrantFiled: February 20, 2001Date of Patent: April 1, 2008Assignee: SanDisk CorporationInventors: Khushrav S. Chhor, Tae-Hee Lee
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Patent number: 7005730Abstract: A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may include the capability to utilize bonding pads on all four sides of an integrated circuit. A lead frame structure may be divided into first and second portions. The first portion may be adapted to receive the stacked integrated circuits and the second portion may include a plurality of conductors. The first portion may also be adapted to couple at least one of the integrated circuits to power and ground conductors on the second portion. In one embodiment, the first portion may include the lead frame paddle and a conductive ring. In another embodiment, the first portion may include first and second coplanar elements.Type: GrantFiled: March 4, 2004Date of Patent: February 28, 2006Assignee: Matrix Semiconductor, Inc.Inventors: Vani Verma, Khushrav S. Chhor
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Patent number: 6843421Abstract: An improved memory module and method of manufacture are presented. The memory module takes on the same outer dimensions as conventional memory cards. The memory module includes an integrated circuit and a conductor encased within molded resin. The conductor can be taken from a tape or a lead frame, and can include bumps or wires extending from the conductor to corresponding bonding pads on the integrated circuit. The bonded integrated circuit can thereafter be placed within a cavity formed inside a mold housing, where resin may be injected to form the memory module. The conductor can also be shaped so as to extend on multiple planes from the connection point on or near the bonding pad to an edge connector residing near one edge only of the memory module. The conductor is thereby connected to the integrated circuit and provides slide-in, releasable coupling to a receptor.Type: GrantFiled: August 13, 2001Date of Patent: January 18, 2005Assignee: Matrix Semiconductor, Inc.Inventors: Khushrav S. Chhor, Larry L. Moresco
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Publication number: 20040169285Abstract: A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may include the capability to utilize bonding pads on all four sides of an integrated circuit. A lead frame structure may be divided into first and second portions. The first portion may be adapted to receive the stacked integrated circuits and the second portion may include a plurality of conductors. The first portion may also be adapted to couple at least one of the integrated circuits to power and ground conductors on the second portion. In one embodiment, the first portion may include the lead frame paddle and a conductive ring. In another embodiment, the first portion may include first and second coplanar elements.Type: ApplicationFiled: March 4, 2004Publication date: September 2, 2004Inventors: Vani Verma, Khushrav S. Chhor
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Patent number: 6731011Abstract: A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may include the capability to utilize bonding pads on all four sides of an integrated circuit. A lead frame structure may be divided into first and second portions. The first portion may be adapted to receive the stacked integrated circuits and the second portion may include a plurality of conductors. The first portion may also be adapted to couple at least one of the integrated circuits to power and ground conductors on the second portion. In one embodiment, the first portion may include the lead frame paddle and a conductive ring. In another embodiment, the first portion may include first and second coplanar elements.Type: GrantFiled: February 19, 2002Date of Patent: May 4, 2004Assignee: Matrix Semiconductor, Inc.Inventors: Vani Verma, Khushrav S. Chhor
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Publication number: 20030155659Abstract: A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may include the capability to utilize bonding pads on all four sides of an integrated circuit. A lead frame structure may be divided into first and second portions. The first portion may be adapted to receive the stacked integrated circuits and the second portion may include a plurality of conductors. The first portion may also be adapted to couple at least one of the integrated circuits to power and ground conductors on the second portion. In one embodiment, the first portion may include the lead frame paddle and a conductive ring. In another embodiment, the first portion may include first and second coplanar elements.Type: ApplicationFiled: February 19, 2002Publication date: August 21, 2003Inventors: Vani Verma, Khushrav S. Chhor
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Publication number: 20030029920Abstract: An improved memory module and method of manufacture are presented. The memory module takes on the same outer dimensions as conventional memory cards. The memory module includes an integrated circuit and a conductor encased within molded resin. The conductor can be taken from a tape or a lead frame, and can include bumps or wires extending from the conductor to corresponding bonding pads on the integrated circuit. The bonded integrated circuit can thereafter be placed within a cavity formed inside a mold housing, where resin may be injected to form the memory module. The conductor can also be shaped so as to extend on multiple planes from the connection point on or near the bonding pad to an edge connector residing near one edge only of the memory module. The conductor thereby serves as an integrated signal carrier which receives connection to the integrated circuit and provides slide-in, releasable coupling to a receptor normally designed to receive conventional memory cards.Type: ApplicationFiled: August 13, 2001Publication date: February 13, 2003Inventors: Khushrav S. Chhor, Larry L. Moresco
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Publication number: 20020116668Abstract: By decreasing the amount of card substrate required in a memory card to support the actual memory unit, the test interface of the card, which is usually removed before final assembly of the card, can be brought within the allowable length of the finished card and can, therefore, remain on the card permanently. Consequently, in the event of a field failure, the test interface remains available for testing the card and diagnosing the location and cause of the failure.Type: ApplicationFiled: February 20, 2001Publication date: August 22, 2002Applicant: Matrix Semiconductor, Inc.Inventors: Khushrav S. Chhor, Tae-Hee Lee
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Patent number: 6215689Abstract: Architecture, circuitry, and methods are provided for operating a high speed, volatile programmable logic integrated circuit using back-up non-volatile memory cells configured on an integrated circuit separate from the programmable logic integrated circuit. The lower density non-volatile memory cells can be formed on an integrated circuit using fabrication steps similar to those used to form, e.g., EEPROM devices or, more specifically, flash EEPROM devices. The programmable logic integrated circuit includes high density, volatile memory cells integrated with high speed, low density configurable CMOS-based logic. By using two separate processing technologies on two separate and distinct monolithic substrates, and interconnecting the separate integrated circuits on a singular monolithic substrate, the advantages of non-volatility can be combined with a high speed programmable circuit.Type: GrantFiled: November 18, 1999Date of Patent: April 10, 2001Assignee: Cypress Semiconductor CorporationInventors: Khushrav S. Chhor, Bo Soon Chang, Timothy M. Lacey
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Patent number: 6209110Abstract: An integrated circuit, a programming mechanism and a method are provided for programming test information upon non-volatile storage devices of the integrated circuit. The test information includes a pass/fail outcome arising from one or more test operations to which the integrated circuit is exposed. In addition to or in lieu of the test outcomes, test results of one or more parametric tests at select test operations can be measured from and programmed back into the integrated circuit. Test limits against which the test results can be compared may also be programmed into the integrated circuit. The test outcomes of various test operations, test results of various test parameters and test limits of the same or dissimilar test parameters are stored in separate non-volatile storage locations attributed to the integrated circuit.Type: GrantFiled: March 30, 1998Date of Patent: March 27, 2001Assignee: Cypress Semiconductor CorporationInventors: Khushrav S. Chhor, William R. Orso
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Patent number: 6181615Abstract: An integrated circuit, a programming mechanism and a method is provided for programming test information upon non-volatile storage devices of the integrated circuit. The test information includes a pass/fail outcome arising from one or more test operations to which the integrated circuit is exposed. In addition to or in lieu of the test outcomes, test results of one or more parametric tests at select test operations can be measured from and programmed back into the integrated circuit. Test limits against which the test results can be compared may also be programmed into the integrated circuit. The test outcomes of various test operations, test results of various test parameters and test limits of the same or dissimilar test parameters are stored in separate non-volatile storage locations attributed to the integrated circuit.Type: GrantFiled: March 30, 1998Date of Patent: January 30, 2001Assignee: Cypress Semiconductor CorporationInventor: Khushrav S. Chhor
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Patent number: 6160410Abstract: An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. The insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment.Type: GrantFiled: March 24, 1998Date of Patent: December 12, 2000Assignee: Cypress Semiconductor CorporationInventors: William R. Orso, Khushrav S. Chhor
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Patent number: 6057696Abstract: An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. T he insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment.Type: GrantFiled: March 24, 1998Date of Patent: May 2, 2000Assignee: Cypress Semiconductor Corp.Inventors: William R. Orso, Khushrav S. Chhor, Joseph D. Caliston