Abstract: In an I/O driver, noise reduction is achieved while maintaining good performance, by providing a conventional output driver leg and a secondary output driver leg, the primary output driver leg comprising a primary predriver and a primary output driver, and the secondary output driver leg comprising a secondary output driver having a common output with the primary output driver, wherein feedback from the common output is fed through a pair of pass gates that control the secondary output driver.

Abstract: In an I/O driver that includes a cascoded pair of PMOS driver transistors connected to a pair of cascaded NMOS driver transistors and that defines a pad output between the PMOS and NMOS driver transistors, a method of providing the CMOS I/O driver with over-voltage and back-drive protection includes providing circuitry for charging the wells of the PMOS transistors either to VDDIO during normal voltage mode by making use of the power supply, or to a common voltage during over-voltage and back-drive operation using the pad voltage.

Abstract: A power supply detection circuit biased by at least two power supply voltages for controlling a signal driver circuit. Upstream and downstream amplifiers, powered by upstream and downstream power supply voltages, respectively, process an original control signal to produce a differential signal via output signal electrodes. Capacitances coupling respective ones of the output signal electrodes to the downstream power supply voltage and the circuit reference potential discharge and charge respective ones of the output signal electrodes in relation to initial receptions of the upstream and downstream power supply voltages and original control signal, following which voltage clamp circuitry maintains such discharged and charged states pending reception of the original control signal in a predetermined state.

Abstract: In a high tolerance I/O interface with over-voltage protection beyond 5 V, a cascoded driver with PMOS pull-up and NMOS pull-down transistors, connected to a pad, is provided. Circuitry is included to maintain the floating well voltages of the PMOS pull-up driver transistors at substantially the same voltages as their respective drains, and their gate voltages at substantially the same voltages as their respective drains, under back-drive and 5 V tolerant mode. Circuitry is also provided to increase the gate voltage of one of a cascoded pair of NMOS pull-down driver transistors, so that the drain-source junction voltage and gate oxide voltage of the transistor will be less than the breakdown voltage under back-drive and 5 V tolerant mode.

Abstract: In a VDD detect circuit, the output driver interfaces are disabled during power up by pulling the gates of the PMOS interface transistors high using a additional circuitry that operates when VDD is not asserted. The circuit includes a level shifter for controlling the PMOS and NMOS interface transistors during normal mode, and the additional circuitry includes an inverter and a diode string powered by VDDIO, that provides a reference voltage to the level shifter during power up mode. Current flow through the diode string is disabled by a PMOS transistor controlled by VDD, and current flow through the inverter is disabled by the PMOS transistor of the inverter, which is also controlled by VDD. Thus, the additional circuitry provides the enable signal during power up when VDD is not asserted, and does so without causing additional power consumption during normal mode, since the PMOS transistors prevent additional current flow when VDD is high.

Abstract: The invention enables the performance of the input and output stages of an I/O circuit to be modified after an IC is manufactured. In one embodiment, the I/O circuit includes an output driver, programmable pre-driver, programmable Schmitt-trigger input buffer, control circuit and logic circuit. Depending on the number of pull-up and pull-down MOS transistor pairs or “cells” that are enabled in the programmable pre-driver and their different sizes, the overall sizing ratio imbalance between the transistors may be programmed. In particular, the high and low trip points for activation of the output driver is related to an imbalance in the overall sizing ratio of transistors enabled in the programmable pre-driver. This affects the timing characteristics of the output driver.

Abstract: In a high tolerance I/O interface with over-voltage protection during 5V tolerant mode and back-drive mode, includes pass gate circuitry to isolate the output of the driver circuit and input of the receiver circuit from the pad voltage during stress mode. The gate voltage of the PMOS transistor of the pass gate is charged up to avoid gate oxide breakdown during stress mode. Also, the gate and well of the driver pull-up transistor are charged to NG1 to avoid current flow through the transistor and to its well.

Abstract: An output driver obtains over voltage protection by utilizing a first transistor to pass signals from an internal node to an external node when the driver is transmitting data, and to isolate the internal node from the external node when the driver has stopped transmitting data. When the driver has stopped transmitting data, the voltage on the external node is subject to rising. The output driver also utilizes a second transistor and a resistance to ground to control the first transistor.

Abstract: In a receiver input back-drive protection circuit and method, a pass gate is provided between the high pad voltage and the receiver input and a clamping circuit is provided, to present a reduced voltage to the receiver input during stress mode.

Abstract: A method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device. At least one logic function to be performed by the look-up table is chosen. An output state is determined for each set of inputs to the look-up table, the output state being an array of outputs of the look-up table. Each output state is made up of responses of the chosen logic functions to a particular set of input variables. Identical output states are formed into groups. Selected groups of the output states which do not require programmable architecture elements are eliminated. A programmable architecture element is then assigned for each remaining group of output states.

Abstract: A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.

Abstract: A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

Abstract: A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.

Abstract: A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.