Abstract: According to an example embodiment, a memory diagnosis test circuit may include a memory core block, a word line selector, a bit line selector, and/or an analog mode control unit. The memory core block may include a plurality of memory cells. The word line selector may be configured to select one of a plurality of word lines of the memory core block using a first shift register. The bit line selector may be configured to select one of a plurality of bit line pairs of the memory core block using a second shift register. The analog mode control unit may be configured to monitor data corresponding to the selected word line and bit line pair.

Abstract: In an analytic structure for failure analysis of a semiconductor device, a plurality of analytic regions are arranged in regions of a semiconductor substrate. A plurality of semiconductor transistors having an array structure are arranged in each of the analytic regions. A plurality of interconnection structures connect the semiconductor transistors, each comprising multiple layered metal patterns and multiple layered plugs interposed between the multiple layered metal patterns. A first number of layers of the multiple layered metal patterns and multiple layered plugs is different in one of the analytic regions than a second number of layers of the multiple layered metal patterns and multiple layered plugs in another one of the analytic regions.

Abstract: In a method and structure for semiconductor failure analysis, the structure comprises: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array; wordlines arranged on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a first direction; and bitline structures on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a second direction, wherein the bitline structures are configured in different patterns in each of the plurality of analytic fields.

Abstract: In a test circuit, an oscillation signal is generated based on a design rule pattern of a chip formed on a wafer. The oscillation signal is counted using a counter, and an N-bit signal is generated from the counting of the oscillation signal. The N-bit signal is serialized and output. In a test method, an oscillation signal is generated based on a design rule pattern of a chip formed on a wafer. The oscillation signal is counted, and an N-bit signal is generated based on the counting of the oscillation signal. The N-bit signal is serialized and output.

Abstract: According to an example embodiment, a memory diagnosis test circuit may include a memory core block, a word line selector, a bit line selector, and/or an analog mode control unit. The memory core block may include a plurality of memory cells. The word line selector may be configured to select one of a plurality of word lines of the memory core block using a first shift register. The bit line selector may be configured to select one of a plurality of bit line pairs of the memory core block using a second shift register. The analog mode control unit may be configured to monitor data corresponding to the selected word line and bit line pair.

Abstract: In an analytic structure for failure analysis of a semiconductor device, a plurality of analytic regions are arranged in regions of a semiconductor substrate. A plurality of semiconductor transistors having an array structure are arranged in each of the analytic regions. A plurality of interconnection structures connect the semiconductor transistors, each comprising multiple layered metal patterns and multiple layered plugs interposed between the multiple layered metal patterns. A first number of layers of the multiple layered metal patterns and multiple layered plugs is different in one of the analytic regions than a second number of layers of the multiple layered metal patterns and multiple layered plugs in another one of the analytic regions.

Abstract: In a method and structure for semiconductor failure analysis, the structure comprises: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array; wordlines arranged on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a first direction; and bitline structures on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a second direction, wherein the bitline structures are configured in different patterns in each of the plurality of analytic fields.