Abstract: The present invention provides systems and methods that allow mobile devices, such as PDAs, mobile telephones, and laptops to roam seamlessly between subnets of a mobile wireless network and communicate through the network with local mobile devices and/or Internet sites without having to acquire a new or temporary Internet Protocol (IP) address. The network enables a wireline IP router to support wireless mobile devices. The network performs real-time soft-roaming to enable instantaneous connectivity of a visiting mobile device. Specifically, the network relies on the subnets to share IP addresses of the mobile devices.

Abstract: The present invention provides systems and methods that allow mobile devices, such as PDAs, mobile telephones, and laptops to roam seamlessly between subnets of a mobile wireless network and communicate through the network with local mobile devices and/or Internet sites without having to acquire a new or temporary Internet Protocol (IP) address. The network enables a wireline IP router to support wireless mobile devices. The network performs real-time soft-roaming to enable instantaneous connectivity of a visiting mobile device. Specifically, the network relies on the subnets to share IP addresses of the mobile devices.

Abstract: A natural heat dissipation device for a microprocessor. The microprocessor is conventionally mounted to a printed circuit board. The printed circuit board contains a recess that is cut-out directly below the microprocessor. Heat sink material is attached to the microprocessor through the recess. The heat sink material attached to the bottom of the microprocessor may be used alone or in conjunction with a an attached metal tray or case under the printed circuit board.

Abstract: A volatile memory initialization systems differentiates between a first class of reset causes requiring memory initialization and a second class of reset causes not requiring memory initialization. A register records the first and second classes of reset causes. A volatile memory initialization function is performed when a reset of the first class of reset causes is read from the register. The volatile memory initialization function is bypassed when a reset of the second class of reset causes is read from the register.

Abstract: A system bus architecture for intermodular communications is disclosed. The system bus architecture comprises a backplane bus with associated memory and a plurality of control registers. A master system processor module is coupled to the backplane bus via a master bus controller. The master system processor module contains a central processing unit in selective communication the master bus controller. A plurality of slave modules are also coupled to the backplane bus via respective slave bus controllers. Each of the slave modules has a slave central processing unit in selective communication the slave bus controller. The master and slave bus controllers are in selective communication with the bus memory, the plurality of control registers, and the respective central processing units, to transmit and receive data through the backplane bus.

Abstract: A bus recovery system for multi-master bus system comprises a plurality of bus masters selectively interfacing with a system bus whereby access to the bus is controlled by a bus arbiter. A plurality of counters corresponding to each of the plurality of masters contains a pre-determined time value corresponding to the maximum time each of the plurality of masters may be granted access to bus. The arbiter releases ownership of the bus when the pre-determined time value in the counter has been exceeded by master currently accessing the bus. A register identifies which of the masters had access to the bus when the predetermined time value was exceeded.

Abstract: A natural heat dissipation device for a microprocessor. The microprocessor is conventionally mounted to a printed circuit board. The printed circuit board contains a recess that is cut-out directly below the microprocessor. Heat sink material is attached to the microprocessor through the recess. The heat sink material attached to the bottom of the microprocessor may be used alone or in conjunction with a an attached metal tray or case under the printed circuit board.

Abstract: In a system bus having a master-slave architecture, shared memory controlled by a plurality of registers, master-slave central processing units, and master-slave bus controllers, a process of reading and writing data to the shared memory is disclosed. The process comprises the steps of requesting access to the shared memory by the central processing units by writing a request bit on a first register; reading an access bit on a second register to determine whether the access bit is set and access to shared memory is granted; reading or writing data to the shared memory by the central processing units; and reading the access bit on the second register to determine whether the access bit is cleared and access to the shared memory is complete. The access bit is set by the master-slave bus controller.