Abstract: The present disclosure relates to a brake disc including a braking part having a circular plate shape having a hollow portion and a plurality of coupling portions protruding and extending from an inner diameter surface thereof, and a hat part disposed in the hollow portion and having a plurality of insertion portions protruding laterally, in which the plurality of coupling portions is respectively coupled to the plurality of insertion portions, and the coupling portion of the braking part and the insertion portion of the hat part are joined to only one of an outboard portion or an inboard portion of the braking part. According to the present disclosure, it is possible to reduce noise occurring at a position at which the hat part and the braking part are coupled to each other and improve cooling performance.

Abstract: A method of controlling an EOP of a powertrain may include determining, by a controller electrically connected to the EOP, whether an oil sloshing phenomenon in which it is difficult for oil to return to a space where an oil intake port of the EOP is positioned may occur while a vehicle is running; and reducing, by the controller, the revolutions per minute (RPM) of the EOP by a predetermined reduced RPM when it is determined that the oil sloshing phenomenon may occur.

Abstract: A display device includes light transmitting areas including a first light transmitting area and light emitting areas around the light transmitting areas and including a first light emitting area disposed around the first light transmitting area, wherein the first light emitting area includes a first-first light emitting area adjacent to a first portion of each of the light transmitting areas, a first-second light emitting area adjacent to a second portion of each of the light transmitting areas, a first-third light emitting area adjacent to a third portion of each of the light transmitting areas, and a first-fourth light emitting area disposed adjacent to a fourth portion of each of the light transmitting areas. The first-first to first-fourth light emitting areas each include at least one of first to third light emitting portions to emit light of first to third colors, respectively.

Abstract: A display device includes a substrate, a first electrode and a second electrode which are spaced apart from each other in a second direction, light-emitting elements spaced apart from each other in the first direction, a first contact electrode electrically contacting the light-emitting elements, and a second contact electrode electrically contacting the light-emitting elements. The first contact electrode electrically contacts the first electrode through a first contact portion disposed on the first electrode, the second contact electrode electrically contacts the second electrode through a second contact portion disposed on the second electrode, the first contact portion is disposed on an end portion in the first direction of the first contact electrode, and the second contact portion is disposed on an end portion in the first direction of the second contact electrode.

Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.

Abstract: A three dimensional scaffold for generating cell or protein assemblies. This degradable scaffold can be applied to various types of cells. Also disclosed are methods of treating a condition by implanting the protein or cell assembly prepared according to the method described herein.

Abstract: A dynamic interference lithography (DIL) device is provided. The device includes a laser source configured for providing a laser beam, a substrate stage configured for mounting a substrate, an at least partially convex curved mirror, and a spatial filter configured to divide the laser beam into a first beam portion directed towards the at least partially convex curved mirror and a second beam portion directed towards the substrate. The first beam portion is reflected by the at least partially convex curved mirror towards the substrate to form an interference pattern on the substrate.

Abstract: A surface-enhanced Raman scattering (SERS) sensing system or platform and methods of using the same, where the platform comprises a graphene coated-homogeneous plasmonic metal hybrid array, which synergizes both electromagnetic mechanism (EM)- and chemical mechanism (CM)-based signal enhancement for achieving sensitive and reproducible detection of Raman signals. The system and methods of using such system or platform may be applied to the analyses of various bio/chemical molecules, such as but not limited to those found in cells, in a highly sensitive and selective manner.

Abstract: This application discloses the compositions comprising biologically active synthetic nanoparticle constructs and methods of use thereof to modify gene expression including transcriptional activation and transcriptional repression.

Abstract: Disclosed are spheroidal hybrid biodegradable materials containing low dimensional manganese dioxide (MnO2) support structures and cells, methods of manufacture thereof, and methods of use thereof.

Abstract: A method of determining a marker layout for a semiconductor device includes determining the number of markers to be used in a field of a wafer using a first fitness function, calculating a marker probability distribution considering distance information among the markers and determining locations of a marker to be used according to the marker probability distribution, and evaluating performance of a final marker layout by using a second fitness function. The method provides an optimized approach to marker layout, so that the quality of a marker layout may be enhanced. Also, the method generates a marker layout that may minimize a prediction value of an overlay error of experimental wafers and an irregularity of marker locations, so that robust performance may be ensured for the prediction of overlay errors for subsequent new wafers.

Abstract: Provided in the present specification is an ETV2 transcription factor comprising: a polyamide comprising a domain binding to DNA (DNA binding domain) of an ETV2 gene; a nuclear localization signal peptide; and a nano-particle.

Abstract: Nanorod devices for isolating and characterizing target cellular components are provided. Methods of isolating, detecting, and/or characterizing the components are also provided. Methods of use and treatment are further disclosed, such as treating diseases identified using the nanorods and/or using differentiated stem cells identified using the provided nanorods.

Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.

Abstract: Disclosed herein are embodiments of a composition comprising at least three layers. Layers one and two each either comprises a sensitizer or an emitter, typically a metal ion or a dye, and the third layer may or may not comprise a sensitizer or emitter. Upon exposure to light, such as infrared light, the composition produces visible and/or UV light. The composition may further comprise a capping moiety, a therapeutic agent, an uptake enhancer, a detection moiety that binds to a desired target, a quenching moiety, or a combination thereof. The composition may be a particle, such as a nanoparticle, or it may be a planar composition. Also disclosed are embodiments of a method for using the composition, including, but not limited to, a method for delivering a therapeutic agent, or a method for detecting a target, such as a biological target.

Abstract: A method of determining a marker layout for a semiconductor device includes determining the number of markers to be used in a field of a wafer using a first fitness function, calculating a marker probability distribution considering distance information among the markers and determining locations of a marker to be used according to the marker probability distribution, and evaluating performance of a final marker layout by using a second fitness function. The method provides an optimized approach to marker layout, so that the quality of a marker layout may be enhanced. Also, the method generates a marker layout that may minimize a prediction value of an overlay error of experimental wafers and an irregularity of marker locations, so that robust performance may be ensured for the prediction of overlay errors for subsequent new wafers.

Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.

Abstract: The invention relates to biodegradable nanoscaffolds, e.g. low dimension manganese oxide (MnO2)-based nanoscaffolds containing ECM proteins and/or cationic polymers, and methods of use and manufacture thereof.

Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.