Abstract: A battery module and a battery pack including the same are disclosed. In some implementations, the battery module may include a plurality of battery cells; and a cell monitoring portion connected to the plurality of battery cells, the cell monitoring portion including a plurality of boards collecting information on at least one of temperature, current, and voltage of the plurality of battery cells. The plurality of boards may be separable.

Abstract: A surface-emitting laser package comprises: a substrate; a surface-emitting laser device disposed on the substrate, and having a non-emitting area and an emitting area which includes a plurality of emitters each generating a first laser beam; a housing disposed around the surface-emitting laser device; and a diffusing part disposed on the surface-emitting laser device. The emitting area has a first width in a first direction and a second width in a second direction perpendicular to the first direction, and the second width may be greater than the first width. The diffusing part outputs the first laser beam into a second laser beam having a first angle of view in the first direction and a second angle of view in the second direction, and the first angle of view may be greater than the second angle of view.

Abstract: The present invention relates to an apparatus and a method capable of calculating insulation resistances and parasitic capacitances of a battery outside the battery. In the present invention, when a positive electrode connector and a negative electrode connector are coupled to a positive electrode terminal and a negative electrode terminal of the battery, respectively, and a ground connector is coupled to a case of the battery, even though the battery is positioned inside a chamber in order to perform a temperature test or the like of the battery, the insulation resistances and the parasitic capacitances of the battery may be calculated without needing to move the battery to the outside of the chamber. Accordingly, the insulation resistances and the parasitic capacitances of the battery may be conveniently calculated.

Abstract: A management system and a control method are disclosed to transmit/share fault state information immediately without constructing a separate communication path for transmitting fault state information.

Abstract: A battery system includes first to N-th battery modules sequentially connected in a daisy chain configuration; and a master controller connected to the first battery module through an interface IC, selecting at least one target module among the first to N-th battery modules, and transmitting a control command for the target module. The target module unidirectionally transmits the control command received from the master controller, and bidirectionally transmits response data generated in response to the control command. The master controller selects the N-th battery module as the target module first, and selects the first battery module as the target module last.

Abstract: A transmission/reception method and device for isolated communication is proposed. The transmission/reception method includes performing transmission, wherein bit streams are extracted from data and two or more predetermined number of bits are modulated into one DC balanced symbol so as to generate a signal in which a plurality of symbols are listed, thereby transmitting the signal through an isolated communication circuit, and performing reception, wherein the signal is received through the isolated communication circuit and the plurality of symbols included in the signal are demodulated into the two or more predetermined number of bits so as to generate the bit streams and organize the bit streams into the data. The transmission/reception method and device may reduce power consumption at the same communication speed because a plurality of bits is represented by the one DC balanced symbol.

Abstract: A battery management system includes a microcontroller unit which transmits and receives communications information through a communications input/output terminal, a fault generator unit which generates fault information and transmits the fault information through a fault information output terminal, and a battery cell monitoring unit which is coupled to the communications input/output terminal and the fault information output terminal and diagnoses an operation of internal function based on the fault information transmitted from the fault generator unit and outputs an internal diagnosis result value to the microcontroller unit.

Abstract: The present invention relates to an apparatus and a method capable of calculating insulation resistances and parasitic capacitances of a battery outside the battery. In the present invention, when a positive electrode connector and a negative electrode connector are coupled to a positive electrode terminal and a negative electrode terminal of the battery, respectively, and a ground connector is coupled to a case of the battery, even though the battery is positioned inside a chamber in order to perform a temperature test or the like of the battery, the insulation resistances and the parasitic capacitances of the battery may be calculated without needing to move the battery to the outside of the chamber. Accordingly, the insulation resistances and the parasitic capacitances of the battery may be conveniently calculated.

Abstract: The present invention relates to an apparatus and a method capable of calculating insulation resistances and parasitic capacitances of a battery outside the battery. In the present invention, when a positive electrode connector and a negative electrode connector are coupled to a positive electrode terminal and a negative electrode terminal of the battery, respectively, and a ground connector is coupled to a case of the battery, even though the battery is positioned inside a chamber in order to perform a temperature test or the like of the battery, the insulation resistances and the parasitic capacitances of the battery may be calculated without needing to move the battery to the outside of the chamber. Accordingly, the insulation resistances and the parasitic capacitances of the battery may be conveniently calculated.

Abstract: A semiconductor device disclosed in an embodiment comprises: a light emitting unit comprising a light emitting structure layer which has a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; and a sensor unit disposed on the light emitting unit, wherein the sensor unit comprises: a sensing material changing in resistance with light emitted by the light emitting unit; a first sensor electrode comprising a first pad portion and a first extension part extending from the first pad portion and contacting the sensing material; and a second sensor electrode comprising a first pad portion and a second extension part extending toward the first extension part from the second pad portion and contacting the sensing material. The sensor unit senses an external gas in response to the light generated from the light emitting unit.

Abstract: The present disclosure relates to a battery cell monitoring unit having a fault injection terminal and a battery management system using the same. The battery management system includes: a microcontroller unit transmitting and receiving communications information through a communications input/output terminal; a fault generator unit generating fault information and transmitting the fault information through a fault information output terminal; and a battery cell monitoring unit coupled to the communications input/output terminal and the fault information output terminal, and configured to diagnose an operation of internal function based on the fault information transmitted from the fault generator unit and to output an internal diagnosis result value to the microcontroller unit.

Abstract: A surface-emitting laser package comprises: a substrate; a surface-emitting laser device disposed on the substrate, and having a non-emitting area and an emitting area which includes a plurality of emitters each generating a first laser beam; a housing disposed around the surface-emitting laser device; and a diffusing part disposed on the surface-emitting laser device. The emitting area has a first width in a first direction and a second width in a second direction perpendicular to the first direction, and the second width may be greater than the first width. The diffusing part outputs the first laser beam into a second laser beam having a first angle of view in the first direction and a second angle of view in the second direction, and the first angle of view may be greater than the second angle of view.

Abstract: A semiconductor device disclosed in an embodiment comprises: a light emitting unit comprising a light emitting structure layer which has a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; and a sensor unit disposed on the light emitting unit, wherein the sensor unit comprises: a sensing material changing in resistance with light emitted by the light emitting unit; a first sensor electrode comprising a first pad portion and a first extension part extending from the first pad portion and contacting the sensing material; and a second sensor electrode comprising a first pad portion and a second extension part extending toward the first extension part from the second pad portion and contacting the sensing material. The sensor unit senses an external gas in response to the light generated from the light emitting unit.

Abstract: Disclosed is a semiconductor manufacturing apparatus including at least one pocket on which a passive subject on which deposition will be executed is mounted, and a carrier body having an insertion space to which the at least one pocket is detachably attached. Therefore, the semiconductor manufacturing apparatus shortens process time and reduces process expenses. The semiconductor manufacturing apparatus allows respective pockets to have different structures according to the positions of the pockets on the wafer carrier, and thus achieves uniform growth of a material on the surfaces of wafers regardless of the positions of the pockets.

Abstract: Disclosed is a semiconductor manufacturing apparatus including at least one pocket on which a passive subject on which deposition will be executed is mounted, and a carrier body having an insertion space to which the at least one pocket is detachably attached. Therefore, the semiconductor manufacturing apparatus shortens process time and reduces process expenses. The semiconductor manufacturing apparatus allows respective pockets to have different structures according to the positions of the pockets on the wafer carrier, and thus achieves uniform growth of a material on the surfaces of wafers regardless of the positions of the pockets.

Abstract: A lead frame includes a plurality of leads electrically connected to a semiconductor chip and a lead lock including a base layer disposed over the plurality of the leads and formed of a material having a coefficient of thermal expansion similar to that of inner leads. An adhesive layer is disposed between the base layer and the plurality of leads to fix the plurality of leads and adhere the base layer to the leads. At least one line electrically connects the semiconductor chip to the base layer of the lead lock. Since regions for bus bars are replaced by the lead lock and are removed, the lead frame can be miniaturized and has superior thermal stability and dimension stability.

Abstract: A lead frame includes a plurality of leads electrically connected to a semiconductor chip and a lead lock including a base layer disposed over the plurality of the leads and formed of a material having a coefficient of thermal expansion similar to that of inner leads. An adhesive layer is disposed between the base layer and the plurality of leads to fix the plurality of leads and adhere the base layer to the leads. At least one line electrically connects the semiconductor chip to the base layer of the lead lock. Since regions for bus bars are replaced by the lead lock and are removed, the lead frame can be miniaturized and has superior thermal stability and dimension stability.

Abstract: A lead frame includes a plurality of leads electrically connected to a semiconductor chip and a lead lock including a base layer disposed over the plurality of the leads and formed of a material having a coefficient of thermal expansion similar to that of inner leads. An adhesive layer is disposed between the base layer and the plurality of leads to fix the plurality of leads and adhere the base layer to the leads. At least one line electrically connects the semiconductor chip to the base layer of the lead lock. Since regions for bus bars are replaced by the lead lock and are removed, the lead frame can be miniaturized and has superior thermal stability and dimension stability.

Abstract: A lead frame includes a plurality of leads electrically connected to a semiconductor chip and a lead lock including a base layer disposed over the plurality of the leads and formed of a material having a coefficient of thermal expansion similar to that of inner leads. An adhesive layer is disposed between the base layer and the plurality of leads to fix the plurality of leads and adhere the base layer to the leads. At least one line electrically connects the semiconductor chip to the base layer of the lead lock. Since regions for bus bars are replaced by the lead lock and are removed, the lead frame can be miniaturized and has superior thermal stability and dimension stability.

Abstract: A lead frame includes a plurality of leads electrically connected to a semiconductor chip and a lead lock including a base layer disposed over the plurality of the leads and formed of a material having a coefficient of thermal expansion similar to that of inner leads. An adhesive layer is disposed between the base layer and the plurality of leads to fix the plurality of leads and adhere the base layer to the leads. At least one line electrically connects the semiconductor chip to the base layer of the lead lock. Since regions for bus bars are replaced by the lead lock and are removed, the lead frame can be miniaturized and has superior thermal stability and dimension stability.