Abstract: The present technology relates to a memory device and a method of operating the memory device. The memory device includes a target block manager configured to store a target block address on which a refresh operation is to be performed and output a refresh signal for the target block corresponding to the target block address when an auto refresh command is received, and a data transmission controller configured to output a transmission signal and a buffer control signal for transmitting data between the target block or the buffer block and the temporary buffer circuit in response to the refresh signal.

Abstract: The present technology relates to an electronic device. A memory device performing efficient soft decoding by reducing the number of data provided to a memory controller includes a memory cell array and a page buffer connected to the memory cell array through a bit line. The page buffer includes a plurality of latches and a read data operating component configured to generate a soft bit by logically operating soft data, which are data read from the memory cell array, and to provide the soft bit to a memory controller, in a second read operation performed when a first read operation has failed.

Abstract: The present technology relates to a memory device and a method of operating the memory device. The memory device includes a target block manager configured to store a target block address on which a refresh operation is to be performed and output a refresh signal for the target block corresponding to the target block address when an auto refresh command is received, and a data transmission controller configured to output a transmission signal and a buffer control signal for transmitting data between the target block or the buffer block and the temporary buffer circuit in response to the refresh signal.

Abstract: A nonvolatile memory device may include a cell string comprising a plurality of memory cells coupled in series; a bit line coupled to the cell string; a page buffer suitable for driving a sensing node to a ground voltage, a middle voltage, and a core voltage during a normal program operation, a slow program operation and a program inhibition operation, respectively; and a connection unit suitable for coupling the bit line to the sensing node in response to a control signal of a first voltage during the slow program operation, and in response to the control signal of a second voltage higher than the first voltage during the normal program operation and the program inhibition operation.

Abstract: A nonvolatile memory device may include a cell string comprising a plurality of memory cells coupled in series; a bit line coupled to the cell string; a page buffer suitable for driving a sensing node to a ground voltage, a middle voltage, and a core voltage during a normal program operation, a slow program operation and a program inhibition operation, respectively; and a connection unit suitable for coupling the bit line to the sensing node in response to a control signal of a first voltage during the slow program operation, and in response to the control signal of a second voltage higher than the first voltage during the normal program operation and the program inhibition operation.