Abstract: The in-loop filtering method performed by a video decoding apparatus includes: classifying reconstructed samples according to an absolute classification standard or relative classification standard; acquiring offset data on the basis of results of classifying the reconstructed samples; adding an offset value to the reconstructed samples by referencing the acquired offset data; and outputting the offset value-added reconstructed samples. Accordingly, W errors in the reconstructed image can be corrected.

Abstract: An image encoding/decoding method using a pixel value range constituting an image is disclosed, wherein the image decoding method using a pixel value range constituting an image comprises the steps of: receiving a bitstream; acquiring information of a pixel value range forming a first unit image included in the received bitstream; and decoding the first unit image on the basis of the acquired information of the pixel value range. Therefore, compression efficiency can be improved in an image encoding or decoding process.

Abstract: Disclosed is a decoding method which uses an intra-screen prediction. A decoding method which uses an intra prediction performed in a decoding apparatus comprises the steps of: receiving a bit stream; obtaining decoding information from the received bit stream; generating a prediction block for a current block to be decoded using the obtained decoding information; and restoring the current block by adding a residual block obtained from the bit stream and the prediction block. Accordingly, a compression ratio of an image can be improved.

Abstract: A method for decoding an image based on an intra prediction, comprising: obtaining a first prediction pixel of a first region in a current block by using a neighboring pixel adjacent to the current block; obtaining a second prediction pixel of a second region in the current block by using the first prediction pixel of the first region; and decoding the current block based on the first and the second prediction pixels.

Abstract: Provided is a semiconductor memory device and method of fabricating the semiconductor memory device. A semiconductor memory device includes a gate stack and a plurality of channel structures. The gate stack includes a plurality of stacked conductive patterns spaced apart from each other. The plurality of the channel structures is formed through the gate stack. Each of the channel structures includes a first channel pillar, a second channel pillar and a gate insulation layer. The first channel pillar is formed through the conductive patterns except for an uppermost conductive pattern. The second channel pillar is formed through the uppermost conductive pattern. The second channel pillar is configured to make contact with the first channel pillar. The gate insulation layer is interposed between the uppermost conductive pattern and the first and second channel pillars.

Abstract: A semiconductor integrated circuit device including a semiconductor substrate, a first transistor, an insulation interlayer and a second transistor. The first transistor formed on the semiconductor substrate. The first transistor includes a horizontal channel substantially parallel to a surface of the semiconductor substrate. The insulating interlayer formed on an upper surface of the semiconductor substrate. A contact hole formed through the insulating interlayer. The second transistor including a channel layer formed in the contact hole. Any one of a source and a drain of the second transistor are electrically connected to any one of electrodes of the first transistor.

Abstract: A semiconductor memory device including a gate stack and a plurality of channel structures. The gate stack includes a plurality of stacked conductive patterns spaced apart from each other. The plurality of the channel structures are formed through the gate stack. Each of the channel structures includes a first channel pillar, a second channel pillar and a gate insulation layer. The first channel pillar is formed through the conductive patterns except for an uppermost conductive pattern. The second channel pillar is formed through the uppermost conductive pattern. The second channel pillar is configured to make contact with the first channel pillar. The gate insulation layer is interposed between the uppermost conductive pattern and the first and second channel pillars.