Abstract: A semiconductor device includes a usable address storage unit for selectively storing addresses of a plurality of memory sets using read data of the plurality of memory sets outputted from a nonvolatile memory during a boot-up operation; a register unit for storing the read data of the plurality of memory sets outputted from the nonvolatile memory during the boot-up operation; and an internal circuit for operating by using the read data of the plurality of memory sets stored in the register unit. Addresses corresponding to usable memory sets excluding already-used memory sets and defective memory sets among the memory sets of the nonvolatile memory are extracted and stored, and thus, although an address is not separately inputted when the nonvolatile memory is programmed, data may be programmed in a programmable (usable) memory set.

Abstract: A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips includes a delay chain. Each of the plurality of stacked chips comprises a plurality of Through-Vias, wherein one of the plurality of Through-Vias formed in a first one of the plurality of stacked chips and electrically coupled to a predetermined location of a first delay chain on the first one of the plurality of stacked chips and one of the plurality of Through-Vias formed in a neighboring one of the plurality of stacked chips and electrically coupled to a predetermined location of a delay chain on the neighboring one of the plurality of stacked chips are configured to electrically couple the first one of the plurality of stacked chips to the neighboring one of the plurality of stacked chips. A signal transmitted from a first one of the plurality of stacked chips generates a feedback signal to the first one of the plurality of stacked chips through one or more of the plurality of Through-Vias.

Abstract: A nonvolatile memory includes a plurality of memory sets, wherein each of the memory sets includes a fir memory cell suitable for storing validity signal indicating data validity of the corresponding memory set, and second memory cells suitable for storing multi-bit data or one or more-bit defect information.

Abstract: A nonvolatile memory includes a plurality of memory sets, wherein each of the memory sets includes a first memory cell suitable for storing a validity signal indicating data validity of the corresponding memory set, and second memory cells suitable for storing multi-bit data or one or more-bit defect information.

Abstract: A memory system may include a memory including a cell array having a plurality of word lines and an address storage unit that stores an address in response to a capture command, wherein the memory sequentially refreshes the word lines in response to a refresh command at a set cycle, and refreshes a word line corresponding to the stored address in response to the refresh command when the address is stored in the address storage unit; and a memory controller transmitting the refresh command to the memory at the set cycle when a word line satisfying one or more of conditions that the number of activation times is equal to or more than a reference number and an activation frequency is equal to or more than a reference frequency is detected, and transmitting the capture command and an address of the detected word line to the memory.

Abstract: A memory device including a first cell block including a plurality of word lines and first to Kth (K is a natural number) redundancy word lines, a second cell block including a plurality of word lines and (K+1)th to Nth (N is a natural number greater than K) redundancy word lines, and a control unit suitable for performing control so that the first to Nth redundancy word lines replace the word lines of the first or second cell block, refreshing the word lines of the first and the second cell blocks simultaneously in a first section, and sequentially refreshing the first to Nth redundancy word lines in a second section.

Abstract: A strobe signal generation device includes an enable signal generating section, a buffering section and a strobe signal driving section. The enable signal generation section generates a division enable signal in response a strobe signal. The buffering section configured to generate a delayed strobe signal from the strobe signal while the division enable signal is enabled. The strobe signal driving section configured to generate a plurality of data strobe signals with a larger pulse width than the delayed strobe signal, in response to the division enable signal and the delayed strobe signal.

Abstract: An address detection circuit comprises first to N-th address storage units suitable for storing an address, first to N-th calculation units each suitable for performing a counting operation when an address is stored in a corresponding address storage unit among the address storage units or the address stored in the corresponding address storage unit is inputted, a control unit suitable for sequentially storing an input address in the address storage units, and storing the input address in a selected address storage unit among the address storage units when of the address storage units each store an address, and a detection unit suitable for detecting an address, which is inputted a reference number of times or more, among the addresses stored in the address storage units, based on outputs of the calculation units.

Abstract: A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips includes a delay chain. Each of the plurality of stacked chips comprises a plurality of Through-Vias, wherein one of the plurality of Through-Vias formed in a first one of the plurality of stacked chips and electrically coupled to a predetermined location of a first delay chain on the first one of the plurality of stacked chips and one of the plurality of Through-Vias formed in a neighboring one of the plurality of stacked chips and electrically coupled to a predetermined location of a delay chain on the neighboring one of the plurality of stacked chips are configured to electrically couple the first one of the plurality of stacked chips to the neighboring one of the plurality of stacked chips. A signal transmitted from a first one of the plurality of stacked chips generates a feedback signal to the first one of the plurality of stacked chips through one or more of the plurality of Through-Vias.

Abstract: Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits.

Abstract: A memory system may include a memory including a cell array having a plurality of word lines and an address storage unit that stores an address in response to a capture command, wherein the memory sequentially refreshes the word lines in response to a refresh command at a set cycle, and refreshes a word line corresponding to the stored address in response to the refresh command when the address is stored in the address storage unit; and a memory controller transmitting the refresh command to the memory at the set cycle when a word line satisfying one or more of conditions that the number of activation times is equal to or more than a reference number and an activation frequency is equal to or more than a reference frequency is detected, and transmitting the capture command and an address of the detected word line to the memory.

Abstract: An address detection circuit comprises first to N-th address storage units suitable for storing an address, first to N-th calculation units each suitable for performing a counting operation when an address is stored in a corresponding address storage unit among the address storage units or the address stored in the corresponding address storage unit is inputted, a control unit suitable for sequentially storing an input address in the address storage units, and storing the input address in a selected address storage unit among the address storage units when of the address storage units each store an address, and a detection unit suitable for detecting an address, which is inputted a reference number of times or more, among the addresses stored in the address storage units, based on outputs of the calculation units.

Abstract: A strobe signal generation device includes an enable signal generating section, a buffering section and a strobe signal driving section. The enable signal generation section generates a division enable signal in response a strobe signal. The buffering section configured to generate a delayed strobe signal from the strobe signal while the division enable signal is enabled. The strobe signal driving section configured to generate a plurality of data strobe signals with a larger pulse width than the delayed strobe signal, in response to the division enable signal and the delayed strobe signal.

Abstract: A memory system includes a semiconductor memory including a storage unit configured to store parameter information in response to a test mode signal and to output the stored parameter information in response to a parameter request signal, and a memory controller configured to provide the parameter request signal to the semiconductor memory and receive the parameter information from the semiconductor memory device.

Abstract: A nonvolatile memory includes a plurality of memory sets, wherein each of the memory sets includes a first memory cell suitable for storing a validity signal indicating data validity of the corresponding memory set, and second memory cells suitable for storing multi-bit data or one or more-bit defect information.

Abstract: A system includes a first chip configured to supply a training command and a second chip configured to transfer to the first chip a measured time for performing an operation in response to the training command.

Abstract: An operating method of a memory device includes entering a repair mode, receiving an active command and a fail address, and temporarily storing the received command and address, receiving a write command, and determining whether to perform a program operation, when the program operation is determined to be performed, programming the temporarily-stored fail address into a programmable storage unit, and receiving a precharge command before the programming of the temporarily-stored fail address is completed.

Abstract: An operating method of a memory device includes entering a repair mode, receiving an active command and a fail address, and temporarily storing the received command and address, receiving a write command, and determining whether to perform a program operation, when the program operation is determined to be performed, programming the temporarily-stored fail address into a programmable storage unit, and receiving a precharge command before the programming of the temporarily-stored fail address is completed.

Abstract: A memory system includes a semiconductor memory including a storage unit configured to store parameter information in response to a test mode signal and to output the stored parameter information in response to a parameter request signal, and a memory controller configured to provide the parameter request signal to the semiconductor memory and receive the parameter information from the semiconductor memory device.

Abstract: A memory controller may include a reception unit configured to receive count information on the number of failed addresses in a memory, an address generation unit configured to generate an address having a value between a minimum address value and a maximum address value, wherein the maximum address value is adjusted based on an original maximum value and the count information, and a transmission unit configured to transmit the generated address to the memory.