Abstract: An address comparator circuit includes a first determination unit suitable for activating a first control signal when a first address corresponding to a previous read command is identical with a second address corresponding to a current read command; a second determination unit suitable for activating a second control signal when the previous and current read commands are consecutively inputted to the address comparator circuit with an interval of a specific number of clocks or less; and a blocking signal generation unit suitable for generating a blocking signal that blocks data transmission between a memory array and an external device based on the first and the second control signals.

Abstract: A signal compensation circuit includes a first path configured to cause a source signal to pass therethrough and be outputted as a first signal; a delay block configured to output a second signal by delaying the source signal by a predetermined time; a second path configured to cause the second signal to pass therethrough and be outputted as a third signal; and a signal combination block configured to generate a compensated signal by combining the first signal and the third signal.

Abstract: An address comparator circuit includes a first determination unit suitable for activating a first control signal when a first address corresponding to a previous read command is identical with a second address corresponding to a current read command; a second determination unit suitable for activating a second control signal when the previous and current read commands are consecutively inputted to the address comparator circuit with an interval of a specific number of clocks or less; and a blocking signal generation unit suitable for generating a blocking signal that blocks data transmission between a memory array and an external device based on the first and the second control signals.

Abstract: A data output circuit may include a first node, which receives a first strobe signal, a second node, which receives a second strobe signal, an input control unit that is coupled to the first and second nodes, and receives the first strobe signal generated from a single strobe signal transmitted through a first path of a semiconductor memory apparatus and the second strobe signal generated from the single strobe signal transmitted from a second path of the semiconductor memory apparatus in response to a read command, generates a first input control signal based on the first strobe signal and the second strobe signal, and generates a second input control signal based on the second strobe signal.

Abstract: A memory device include a memory array, a transmitter suitable for outputting data to the outside of the memory device, and a data bus suitable for transmitting data of a selected memory cell in the memory array to the transmitter during a read operation. When successive read commands for the same memory cell are applied, data transmission from the memory array to the data bus is blocked, and data previously loaded in the data bus is outputted through the transmitter.

Abstract: A memory device include a memory array, a transmitter suitable for outputting data to the outside of the memory device, and a data bus suitable for transmitting data of a selected memory cell in the memory array to the transmitter during a read operation. When successive read commands for the same memory cell are applied, data transmission from the memory array to the data bus is blocked, and data previously loaded in the data bus is outputted through the transmitter.

Abstract: A semiconductor memory device includes a first group configured to include a first bank and a second bank; a second group configured to include a third bank and a fourth bank; an address strobe pulse generating unit configured to generate an address strobe pulse signal for activating the first group and the second group in response to a first bank address and a command signal; and a strobe signal generating unit configured to generate a strobe signal that selects a bank from the first group and the second group in response to the address strobe pulse signal and a second bank address.

Abstract: A semiconductor memory device includes a first group configured to include a first bank and a second bank; a second group configured to include a third bank and a fourth bank; an address strobe pulse generating unit configured to generate an address strobe pulse signal for activating the first group and the second group in response to a first bank address and a command signal; and a strobe signal generating unit configured to generate a strobe signal that selects a bank from the first group and the second group in response to the address strobe pulse signal and a second bank address.

Abstract: A semiconductor IC device which includes a common column signal generating block and a column strobe signal generating block. The common signal generating block can provide precolumn strobe signals by using external command signals and a first group of bank addresses among a plurality of bank addresses. The column strobe signal generating block can provide a plurality of column strobe signals to selectively activate a plurality of banks by using the precolumn strobe signals and a second group of bank addresses among the plurality of bank addresses that are not used when the precolumn strobe signals are generated.

Abstract: A semiconductor memory device can output data according to a predetermined data output timing, in spite of a high frequency of system clock, even when a delay locked loop is disabled. The semiconductor memory device includes a delay locked loop configured to perform a delay locking operation on an internal clock to output delay locked clock, and a data output control unit configured to determine a data output timing, according to whether the delay locked loop is enabled or disabled, in response to a read command.

Abstract: A semiconductor memory device includes an input/output line of a data transfer path and its surrounding circuits, comprising a controller which generates a control signal corresponding to command and address input in read and write operation; and a repeater which selects any one of the plurality of bank groups as the control signal to control data transfer between the selected bank group and an input/output pad.

Abstract: The present invention describes a semiconductor memory device that can reduce current consumption occurring in a data write path. The semiconductor memory device includes a write path over which any one of general data and representative data corresponding to a particular mode is transferred in correspondence with a prescribed pad. A routing controller allows the representative data to be routed over a transfer path corresponding to any other pads in the particular mode and prevents the general data from being routed over the transfer path in modes other than the particular mode. The semiconductor memory device can reduce current consumption caused by unnecessary toggling of the data through utilization of the routing controller.

Abstract: A semiconductor memory device capable of reducing a whole area thereof includes a plurality of data input circuits configured to reflect inversion information on data inputted thereto, a plurality of global lines for transferring data outputted from the plurality of data input circuits, and a plurality of memory banks for storing data transferred from the plurality of global lines.

Abstract: The present invention describes a semiconductor memory device having a data mask function and includes a common driving control unit for generating a common driving control signal in response to a data mask signal and a write command signal supplied to the common driving control unit. A plurality of driving units are supplied with the common driving control signal and selectively drive data according to the common driving control signal and transmit the driven data to a plurality of data lines, respectively. Accordingly, a driving and data mask operation of the plurality of driving units is controlled by the common driving control unit, which reduces current consumption and a layout area of the circuit.

Abstract: Disclosed is a semiconductor memory device includes a selector for selectively loading read inversion information and write inversion information on an inversion bus, the inversion bus for transferring the inversion information loaded by the selector, a plurality of read inversion units for reflecting the inversion information from the inversion bus to output data, and a plurality of write inversion units for reflecting the inversion information from the inversion bus to input data.

Abstract: The present invention provides a semiconductor memory device that can reduce unnecessary current consumption, as banks not accessing data maintain an inactivation state and do not receive an input address. A semiconductor memory device includes a plurality of banks grouped into a first group and a second group; and a bank control unit for selecting one of the first group and the second group in response to a bank address to transfer an address to the selected group.

Abstract: A semiconductor memory device includes a plurality of sense amplifiers that amplify data transferred from each of a couple of banks and output them as amplified signals; a controller configured to determine the output states of the amplified signals outputted from each of the couple of sense amplifiers and to output driving signals corresponding to the output amplified signals; and a driver configured to receive driving signals and to drive a global input/output line in response to the driving signals, wherein the couple of sense amplifiers share the one driver.

Abstract: Disclosed is a semiconductor memory device includes a selector for selectively loading read inversion information and write inversion information on an inversion bus, the inversion bus for transferring the inversion information loaded by the selector, a plurality of read inversion units for reflecting the inversion information from the inversion bus to output data, and a plurality of write inversion units for reflecting the inversion information from the inversion bus to input data.

Abstract: A semiconductor IC device includes a common column signal generating block providing precolumn strobe signals by using external command signals and a first group of bank addresses among a plurality of bank addresses, and a column strobe signal generating block providing a plurality of column strobe signals to selectively activate a plurality of banks by using the precolumn strobe signals and a second group of bank addresses among the plurality of bank addresses that are not used when the precolumn strobe signals are generated.

Abstract: A semiconductor memory device capable of reducing a whole area thereof includes a plurality of data input circuits configured to reflect inversion information on data inputted thereto, a plurality of global lines for transferring data outputted from the plurality of data input circuits, and a plurality of memory banks for storing data transferred from the plurality of global lines.