Abstract: Provided is a data strobe signal generating circuit capable of guaranteeing a preamble time (tRPRE). The data strobe signal generating circuit includes: a strobe output driver for outputting a data strobe signal to an outside of a semiconductor device so as to indicate synchronization between an external device and data input/output; and a preamble part for maintaining an output of the strobe output driver to a predetermined logic level during a predetermined delay time from an enabling timing of the preamble signal. Accordingly, it is possible to guarantee the stable operation of the semiconductor memory even when PVT (processor, operating voltage, operating temperature) changes.

Abstract: The present invention relates to a circuit and method for generating an internal clock signal. According to the present invention, it is determined whether an external clock signal is a high frequency or a low frequency. Depending on the determination, the external clock signal is waveform-shaped to generate an internal clock signal or the external clock signal as the internal clock signal as it is. Therefore, rising edge timings of the external clock signal and the internal clock signal become coincident regardless of the frequency of the external clock signal. Reduction in an operating margin within the circuit due to reduction in the pulse width of the internal clock signal is prevented. Thus, the circuit of the present invention can be used in the high frequency and the low frequency at the same time and reliability of the circuit can be improved.

Abstract: A semiconductor memory device including: a plurality of read sense amplifiers for amplifying an output data of a memory cell; a plurality of read delay controllers for delaying an output data of the read sense amplifier by a predetermined time; a plurality of read latches for outputting an output data of the read delay controller as an external data in response to a read strobe signal; a plurality of write sense amplifiers for sensing and amplifying the external data in response to a write strobe signal; a plurality of write delay controllers for delaying an output data of the write sense amplifier by a predetermined time; a plurality of write drivers for inputting an output data of the write delay controller to the memory cell in response to a write enable signal; and a plurality of data buses for transferring the data.

Abstract: The present invention relates to a circuit and method for generating an internal clock signal. According to the present invention, it is determined whether an external clock signal is a high frequency or a low frequency. Depending on the determination, the external clock signal is waveform-shaped to generate an internal clock signal or the external clock signal as the internal clock signal as it is. Therefore, rising edge timings of the external clock signal and the internal clock signal become coincident regardless of the frequency of the external clock signal. Reduction in an operating margin within the circuit due to reduction in the pulse width of the internal clock signal is prevented. Thus, the circuit of the present invention can be used in the high frequency and the low frequency at the same time and reliability of the circuit can be improved.