Abstract: A semiconductor device includes a single crystalline substrate, an electrical element and an optical element. The electrical element is disposed on the single crystalline substrate. The electrical element includes a gate electrode extending in a crystal orientation <110> and source and drain regions adjacent to the gate electrode. The source region and the drain region are arranged in a direction substantially perpendicular to a direction in which the gate electrode extends. The optical element is disposed on the single crystalline substrate. The optical element includes an optical waveguide extending in a crystal orientation <010>.

Abstract: A valve control system may include a latch valve controlling a stream of water in a pipe; a flow rate sensor measuring a flow rate in the pipe; and a valve control device determining that the latch valve is malfunctioning if a flow rate value measured by the flow rate sensor is not within a pre-set flow rate value range corresponding to a valve operation and controlling the latch valve to re-operate in the occurrence of the malfunction, wherein the valve control device may include a first timing device determining the number of re-operations of the latch valve, and wherein when the number of re-operations of the latch valve determined by the first timing device exceeds a pre-set number, the valve control device may control the latch valve to perform a reverse operation of the operation performed during the re-operations.

Abstract: A semiconductor device includes a single crystalline substrate, an electrical element and an optical element. The electrical element is disposed on the single crystalline substrate. The electrical element includes a gate electrode extending in a crystal orientation <110> and source and drain regions adjacent to the gate electrode. The source region and the drain region are arranged in a direction substantially perpendicular to a direction in which the gate electrode extends. The optical element is disposed on the single crystalline substrate. The optical element includes an optical waveguide extending in a crystal orientation <010>.

Abstract: Disclosed are a method of growing a high-quality single layer graphene by using a Cu/Ni multi-layer metallic catalyst, and a graphene device using the same. The method controls and grows a high-quality single layer graphene by using the Cu/Ni multilayer metallic catalyst, in which a thickness of a nickel lower layer is fixed and a thickness of a copper upper layer is changed in a case where a graphene is grown by a CVD method. According to the method, it is possible to obtain a high-quality single layer graphene, and improve performance of a graphene application device by utilizing the high-quality single layer graphene and thus highly contribute to industrialization of the graphene application device.

Abstract: A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.

Abstract: Disclosed herein is an apparatus for driving a motor, including: a rectifying unit rectifying alternative current (AC) input power to generate direct current (DC) power; an inverter applying the DC power to the respective phases of the motor through a switching operation thereof; and a motor driver converting back-electromotive force values sequentially sampled in floating sections of the respective phases into digital values and detecting position information of ZCPs of the respective phases through a pattern of back-electromotive force formed using comparison result values between the digital values and a reference voltage value.

Abstract: A semiconductor device according to example embodiments may include a substrate having an NMOS area and a PMOS area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the isolation regions, source/drain silicide regions formed in the source/drain regions, a tensile stress layer formed on the NMOS area, and a compressive stress layer formed on the PMOS area, wherein the tensile stress layer and compressive stress layer may overlap at a boundary region of the NMOS area and the PMOS area. The semiconductor devices according to example embodiments and methods of manufacturing the same may increase the stress effect on the active region while reducing or preventing surface damage to the active region.

Abstract: There are provided a valve control system, a bidet using the same, and a valve control method. The valve control system includes a latch valve controlling a stream of water in a pipe; a flow rate sensor measuring a flow rate in the pipe; and a valve control device controlling the operation of the latch valve. The valve control device determines whether or not the latch valve is malfunctioning upon analyzing a flow rate measured by the flow rate sensor. When the latch valve is malfunctioning, the valve control device controls the latch valve to re-operate.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a plurality of unit cells provided on a semiconductor substrate. Each of the unit cells may include a buried insulating pattern buried in the semiconductor substrate, a first active pattern provided on the buried insulating pattern, and a second active pattern provided on the buried insulating pattern and spaced apart from the first active pattern. The buried insulating pattern may define a unit cell region, in which each of the unit cells may be disposed.

Abstract: A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer.

Abstract: Methods of manufacturing a semiconductor device including a multi-layer of dielectric layers may include forming a metal oxide layer on a semiconductor substrate and forming a multi-layer of silicate layers including metal atoms and silicon atoms, on the metal oxide layer. The multi-layer of silicate layers may include at least two metallic silicate layers having different silicon concentrations, which are a ratio of silicon atoms among all metal atoms and silicon atoms included in the metallic silicate layer.

Abstract: A logic device may include a first functional block, the first functional block including, a first storage block, a second storage block, and a first function controller. In a first operation time period, the first function controller may be configured to receive a first configuration selection signal and a first configuration command signal that instructs a first function be configured, select the first storage block as a configured storage block in the first operation time period based on the first configuration selection signal, and configure the first function in the first storage block based on the first configuration command signal.

Abstract: A DNA analysis system that controls DNA analysis by wireless using an application of a mobile device and a very small DNA analysis apparatus, and that receives a DNA analysis result in real time on the spot is provided. Therefore, by performing DNA analysis by simultaneously controlling a plurality of small DNA analysis apparatuses using signal processing and screen display functions of a mobile device, analysis speed of DNA is improved, and an analysis result of DNA can be provided in real time. Further, by forming a DNA analysis apparatus in a very small size, DNA can be immediately analyzed with low power consumption on the spot using a small sample, and the DNA analysis apparatus can be carried.

Abstract: A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer.

Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.

Abstract: There is provided a method for controlling a self-generating bidet that can perform power-generation and charging by introduced water and can be stably used. The method for controlling a self-generating bidet comprising a generator, a charging unit, a nozzle part, and a nozzle passage part that is provided between the generator and the nozzle part, the method for controlling the self-generating bidet comprising: a step of sensing the use of the bidet that senses whether the user wishes to use the bidet; and, if it is determined that the user wishes to use the bidet, a step of checking voltage that determines whether the voltage charged in the charging unit is lower than a predetermined reference voltage, and if so, performs power generation through the generator, and charges the charging unit.

Abstract: Disclosed are methods for forming a graphene pattern. The method includes forming a fine pattern defined by at least one trench on a substrate, applying a graphene solution on the fine pattern, and selectively forming a graphene layer on the fine pattern contacting the graphene solution.

Abstract: A gas supply pipe and a chemical vapor deposition (CVD) apparatus including the gas supply pipe. The gas supply pipe includes: a first pipe connected to a gas storage apparatus via a gas supply line to supply a reacting gas into a reacting furnace; and a second pipe thermally contacting the first pipe to cool the first pipe, wherein a first end of the second pipe is connected to a cooling medium supplying unit via a cooling medium line such that a cooling medium circulates inside the second pipe, and a second, opposite end of the second pipe is connected to a cooling medium collecting unit.

Abstract: An apparatus that calculates a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to multiple current frame macroblocks at a time is presented. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in multiple serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation.

Abstract: Disclosed herein are an apparatus and a method for guiding a multi-function switch guide. The apparatus for guiding a multi-function switch includes: a sensor unit that is disposed on an operating lever of a multi-function switch of a vehicle to sense an approach of a user or an operation of the operating lever; a switch state determining unit that determines a current operation state of the multi-function switch, when the approach of the user or the operation of the operating lever is sensed by the sensor unit; an information detection unit that detects a lever operation method corresponding to the current operation state of the multi-function switch; and an output control unit that performs a control to display the detected lever operation method.