Abstract: A semiconductor device may include a gate pattern formed on a semiconductor substrate. At least one impurity region may be formed in the semiconductor substrate such that at least a portion of the at least one impurity region is disposed under the gate pattern. An epitaxial growth layer may be formed on the at least one impurity region. The epitaxial growth layer may include a first epitaxial growth portion spaced apart from the gate pattern and a second epitaxial growth portion extending toward the gate pattern from the first epitaxial growth portion.

Abstract: Methods and apparatus are provided for forming thin films for semiconductor devices, which enable supplying and removing reactants containing constituent elements of a thin film to be formed, by preheating and supplying a process gas and a purging gas at a predetermined temperature in forming the thin film on a substrate. For example, a method for forming a thin film includes supplying a first reactant to a chamber to chemically absorb the first reactant onto a substrate, the first reactant being bubbled by a first gas that is preheated, purging the chamber to remove residues on the substrate having the first reactant chemically absorbed, and forming the thin film by a means of chemical displacement by supplying a second reactant to the chamber to chemically absorb the second reactant onto the substrate.

Abstract: A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a metal-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.

Abstract: A semiconductor device and a method of manufacturing the same, including obtaining a semiconductor substrate, forming a device isolating layer having a depression part and a protrusion part in the semiconductor substrate, forming a gate insulating layer and a gate electrode on the semiconductor substrate, forming a spacer in communication with the gate electrode, removing a portion of the semiconductor substrate to form at least one substrate recess region in an upper surface of the semiconductor substrate and at least one substrate remaining portion extending to a same height as the semiconductor substrate, so that the substrate remaining portion forms a sidewall of the substrate recess region and is in communication with the device isolating layer, and forming a substrate epitaxial layer in the substrate recess region.

Abstract: A semiconductor wafer processing apparatus may include a chuck and/or a focus ring. The chuck may be configured to hold a wafer. The focus ring may be disposed surrounding a rim of the chuck. The focus ring may include a first section formed of a first material and a second section formed of a second material. The first material and the second material may have different conductivities. A method of forming a semiconductor wafer processing apparatus may include forming a first section of a focus ring from a first material, forming a second section of the focus ring from a second material having a different conductivity than the first material, combining the first and second sections to form a focus ring, and/or arranging the focus ring so as to surround a chuck.

Abstract: Methods and apparatus are provided for forming thin films for semiconductor devices, which enable supplying and removing reactants containing constituent elements of a thin film to be formed, by preheating and supplying a process gas and a purging gas at a predetermined temperature in forming the thin film on a substrate. For example, a method for forming a thin film includes supplying a first reactant to a chamber to chemically adsorb the first reactant onto a substrate, the first reactant being bubbled by a first gas that is preheated, purging the chamber to remove residues on the substrate having the first reactant chemically adsorbed, and forming the thin film by a means of chemical displacement by supplying a second reactant to the chamber to chemically adsorb the second reactant onto the substrate.

Abstract: Methods of forming MIM comprise forming a lower electrode on a semiconductor substrate, forming a lower dielectric layer on the lower electrode, and forming an upper dielectric layer on the lower dielectric layer. The lower dielectric layer may be formed of dielectrics having larger energy band gap than that of the upper dielectric layer. An upper electrode is formed on the upper dielectric layer. The upper electrode may be formed of a metal layer having a higher work function than that of the lower electrode.

Abstract: Provided herein are methods of forming a trench including forming a mask layer on a substrate, forming a mask pattern to expose the substrate, using plasma to at least partially remove by-products produced during formation of the mask pattern; and etching the exposed substrate to form a trench having side surfaces including a uniform slope.

Abstract: A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop layer may be formed on the substrate having the auxiliary spacer. The etch stop layer and the auxiliary spacer may be formed of a material having a same stress property.

Abstract: Provided is a microelectromechanical system (MEMS) actuator in which a cantilever piezoelectric actuator and a comb actuator are combined to perform dual shaft drive. The MEMS includes: a stationary comb fixed on a substrate; a movable comb disposed separately from the substrate; and a spring connected to the movable comb and the substrate to resiliently support the movable comb, wherein the movable comb includes a piezoelectric material layer in a laminated manner to be perpendicularly moved by a piezoelectric phenomenon and laterally moved by an electrostatic force to the stationary comb, whereby the MEMS actuator can be used in a driving apparatus of an ultra-slim optical disk drive since the movable comb is made of a piezoelectric material to simultaneously perform focusing actuation to a Z-axis as well as planar actuation.

Abstract: A method of forming a silicon-on-insulator (SOI) semiconductor substrate includes implanting hydrogen ions into a support substrate to form a microbubble layer apart from a surface of the support substrate, forming an SOI layer on the microbubble layer, forming a diffusion barrier layer over the SOI layer, forming a buried oxide layer on a handle substrate, contacting the diffusion barrier layer with the buried oxide layer to be bonded, and annealing the bonded support and handle substrates to separate the support substrate from the SOI layer, wherein the diffusion barrier layer is formed by an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer.

Abstract: A silicon-on-insulator (SOI) semiconductor substrate includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrates an SOI layer formed on the buried oxide layer, and a diffusion barrier layer interposed between the buried oxide layer and the SOI layer, wherein the diffusion barrier layer is an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer.

Abstract: A method of forming a dielectric film composed of metal oxide under an atmosphere of activated vapor containing oxygen. In the method of forming the dielectric film, a metal oxide film is formed on a semiconductor substrate using a metal organic precursor and O2 gas while the semiconductor substrate is exposed under activated vapor atmosphere containing oxygen, and then, the metal oxide film is annealed while the semiconductor substrate is exposed under activated vapor containing oxygen. The annealing may take place in situ with the formation of the metal oxide film, at the same or substantially the same temperature as the metal oxide forming, and/or at least one of a different pressure, oxygen concentration, or oxygen flow rate as the metal oxide forming.

Abstract: A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is formed along an inner wall of the trench and interposed between the trench and the lower portion of the floating gate. A source region is formed in the substrate adjacent a first sidewall of the trench. A control gate having a first portion is formed over the surface of the substrate adjacent a second sidewall of the trench, and a second portion is formed over the upper portion of the floating gate and extending from the first portion. The first sidewall of the trench is opposite the second sidewall of the trench.

Abstract: A method of forming an SOI semiconductor substrate and the SOI semiconductor substrate formed thereby, is provided. The method includes forming sequentially buried oxide, diffusion barrier and SOI layers on a semiconductor substrate. The diffusion barrier layer is formed by an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer. The diffusion barrier layer serves to prevent impurities implanted into the SOI layer from being diffused into the buried oxide layer or the semiconductor substrate.

Abstract: A nonvolatile memory cell array having common drain lines and method of operating the same are disclosed. A positive voltage is applied to a gate of a selected cell and gates of memory cells that share a word line with the selected cell. A first voltage is applied to a drain of the selected cell and drains of the memory cells that share at least a drain line with the selected cell. A second voltage is applied to a source of the selected cell and sources of memory cells that share a bit line with the selected cell, the second voltage being less than the first voltage, such that electrons are injected into the charge storage region of the selected cell to program. A third voltage, which is higher than the second voltage, is applied to bit lines that are not connected to the selected cell.

Abstract: Methods of forming an electronic device include providing a fist electrode, providing a dielectric oxide layer on the first electrode, and providing a second electrode on the dielectric oxide layer so that the dielectric oxide layer is between the first and second electrodes. More particularly, a first portion of the dielectric oxide layer adjacent the first electrode can have a first density of titanium, and a second portion of the dielectric oxide layer opposite the first electrode can have a second density of titanium different than the first density. Related structures are also discussed.

Abstract: The present invention provides organometallic precursors and methods of forming thin films including using the same. The organometallic precursors include a metal and a ligand linked to the metal. The ligand can be represented by the following formula (1): wherein R1 and R2 are each independently hydrogen or an alkyl group. The thin films may be applied to semiconductor structures such as a gate insulation layer of a gate structure and a dielectric layer of a capacitor.

Abstract: A quadrifilar helical antenna comprising two pairs of filars having unequal lengths and phase quadrature signals propagating thereon. A disk-like impedance matching element disposed at a lower end of the antenna matches a source impedance to an antenna impedance. In certain embodiments a first crossbar connector on a substrate disposed at an upper end of the antenna electrically connects two helical filars to form a first filar pair and a second crossbar connector disposed on the substrate connects two filars to form a second filar pair.

Abstract: A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.