Abstract: An airfoil cooling structure, an airfoil having the airfoil cooling structure, and a turbine blade/vane element including the airfoil are disclosed. The airfoil cooling structure includes a cooling path formed inside the airfoil and having a first surface and a second surface opposite to the first surface, and an additive manufactured (AM) feature disposed in the cooling path, manufactured by additive manufacturing, and including a plurality of column parts intersecting with each other so as to abut against the first surface and the second surface.

Abstract: An airfoil having a leading edge and a trailing edge is provided. The airfoil includes a rear cooling path connected to the trailing edge to discharge air to the trailing edge, a plurality of cooling fins formed in the rear cooling path, and a flow guide rod connecting the cooling fins to support the cooling fins, wherein each of the plurality of cooling fins includes an upper fin portion protruding upward from an upper portion of the flow guide rod, a lower fin portion protruding downward from a lower portion of the flow guide rod, and an intermediate fin portion inserted through the flow guide rod.

Abstract: An airfoil having a leading edge and a trailing edge is provided. The airfoil includes a rear cooling path connected to the trailing edge to discharge air to the trailing edge, a plurality of cooling fins formed in the rear cooling path, and a flow guide rod connecting the cooling fins to support the cooling fins, wherein each of the plurality of cooling fins includes an upper fin portion protruding upward from an upper portion of the flow guide rod, a lower fin portion protruding downward from a lower portion of the flow guide rod, and an intermediate fin portion inserted through the flow guide rod.

Abstract: A method for detecting overlay misalignment of a semiconductor device uses a test structure that includes a sensor structure and a via-chain structure. The sensor structure is disposed in a first layer on a semiconductor substrate and includes a plurality of first conductive lines extending in a first direction. Each first conductive line is separated from an adjacent first conductive line in a second direction by a first space. The via-chain structure is in a second layer above the first layer and between the first layer and the second layer. The via-chain structure includes at least one second conductive line disposed in the second layer and at least one via electrically connected to each second conductive line and extending toward the first layer. The at least one via is disposed in the first space between the adjacent first conductive lines of the sensor structure.

Abstract: Disclosed herein is a gas turbine blade. The gas turbine blade includes a turbine blade (33) provided in a turbine, and film cooling elements (100), each including a cooling channel (110) for cooling of the turbine blade (33), an outlet (120) through which cooling air is discharged, and a plurality of ribs (130), wherein the outlet (120) extends from a longitudinally extended end of the cooling channel (110) to an outer surface of the turbine blade (33) and has a width increased from one end of the cooling channel (110) to the outer surface of the turbine blade (33), and the ribs (130) face each other on inner walls of the outlet (120).

Abstract: Disclosed herein is a gas turbine blade. The gas turbine blade includes a turbine blade (33) provided in a turbine, and film cooling elements (100), each including a cooling channel (110) for cooling of the turbine blade (33), an outlet (120) through which cooling air is discharged, and a plurality of ribs (130), wherein the outlet (120) extends from a longitudinally extended end of the cooling channel (110) to an outer surface of the turbine blade (33) and has a width increased from one end of the cooling channel (110) to the outer surface of the turbine blade (33), and the ribs (130) face each other on inner walls of the outlet (120).

Abstract: A method for detecting overlay misalignment of a semiconductor device uses a test structure that includes a sensor structure and a via-chain structure. The sensor structure is disposed in a first layer on a semiconductor substrate and includes a plurality of first conductive lines extending in a first direction. Each first conductive line is separated from an adjacent first conductive line in a second direction by a first space. The via-chain structure is in a second layer above the first layer and between the first layer and the second layer. The via-chain structure includes at least one second conductive line disposed in the second layer and at least one via electrically connected to each second conductive line and extending toward the first layer. The at least one via is disposed in the first space between the adjacent first conductive lines of the sensor structure.

Abstract: A gas turbine blade according to an embodiment of the present invention includes a turbine blade provided in a gas turbine; and a plurality of film coolers formed in a section from a leading edge to a trailing edge of the turbine blade, in which the film cooler includes a cooling channel through which cooling air is introduced and formed in an oval shape; and an outlet through which the cooling air passing through the cooling channel is discharged and extending from an extended end of the cooling channel toward an outer side thereof and formed in an oval shape.

Abstract: An interconnect structure and a method to form an interconnect structure utilizes a high-aspect ratio single-damascene line and a non-damascene via. The interconnect includes a first single-damascene interconnect line disposed in a first interlayer dielectric layer, and a non-damascene via on the first single-damascene interconnect line that may be formed from cobalt, titanium and/or tungsten. A first SiCN layer may be formed on one or more sidewalls of the non-damascene via. A second single-damascene layer may be formed on the non-damascene via in which the second single-damascene layer may be disposed in a second interlayer dielectric layer. A second SiCN layer may be formed on at least part of an upper surface of the first single-damascene layer, and a third SiCN layer may be formed on at least part of an upper surface of the second single-damascene layer.

Abstract: A gas turbine blade according to an embodiment of the present invention includes a turbine blade provided in a gas turbine; and a plurality of film coolers formed in a section from a leading edge to a trailing edge of the turbine blade, in which the film cooler includes a cooling channel through which cooling air is introduced and formed in an oval shape; and an outlet through which the cooling air passing through the cooling channel is discharged and extending from an extended end of the cooling channel toward an outer side thereof and formed in an oval shape.

Abstract: An interconnect structure and a method to form an interconnect structure utilizes a high-aspect ratio single-damascene line and a non-damascene via. The interconnect includes a first single-damascene interconnect line disposed in a first interlayer dielectric layer, and a non-damascene via on the first single-damascene interconnect line that may be formed from cobalt, titanium and/or tungsten. A first SiCN layer may be formed on one or more sidewalls of the non-damascene via. A second single-damascene layer may be formed on the non-damascene via in which the second single-damascene layer may be disposed in a second interlayer dielectric layer. A second SiCN layer may be formed on at least part of an upper surface of the first single-damascene layer, and a third SiCN layer may be formed on at least part of an upper surface of the second single-damascene layer.

Abstract: A microelectronic device includes a dual-damascene interconnect structure and a single-damascene line structure directly on the dual-damascene interconnect structure. The dual-damascene interconnect structure and the single-damascene line structure may each include multiple line segments that are arranged in a brick wall pattern. The brick wall pattern may also be used with two or more single-damascene line structures. Various microelectronic devices and related fabrication methods are described.

Abstract: A microelectronic device includes a dual-damascene interconnect structure and a single-damascene line structure directly on the dual-damascene interconnect structure. The dual-damascene interconnect structure and the single-damascene line structure may each include multiple line segments that are arranged in a brick wall pattern. The brick wall pattern may also be used with two or more single-damascene line structures. Various microelectronic devices and related fabrication methods are described.

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract: A resistor is formed on field oxide with a portion of the resistor body configured to overlap an active region in an integrated circuit (IC) substrate to provide heatsinking for the resistor body. In one embodiment, cooling fingers extend from the resistor body beyond the field oxide to overlap the active region. In another embodiment, minor areas of the resistor body overlap the active region. The resistor body may be formed of polycrystalline silicon (polysilicon), silicided polysilicon, or metal. An oxide having greater thermal conductance than the field oxide is formed between the overlapping parts of the resistor body and the active region.

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract: A resistor is formed on field oxide with a portion of the resistor body configured to overlap an active region in an integrated circuit (IC) substrate to provide heatsinking for the resistor body. In one embodiment, cooling fingers extend from the resistor body beyond the field oxide to overlap the active region. In another embodiment, minor areas of the resistor body overlap the active region. The resistor body may be formed of polycrystalline silicon (polysilicon), silicided polysilicon, or metal. An oxide having greater thermal conductance than the field oxide is formed between the overlapping parts of the resistor body and the active region.

Abstract: A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302. A capping layer 306 is formed the metal line 304. A second dielectric layer 308 is formed over the first dielectric layer 302 and the metal line 304. A first via 310 is formed in the second dielectric layer 308 and in contact with the metal line 304. A second via 312 is formed in the second dielectric layer 308 and in contact with the metal line 304, and is positioned a distance away from the first via 310. An electrically isolated via 326 is formed in the second dielectric layer 308 and in contact with the metal line 304 and in between the first via 310 and the second via 312. A third dielectric layer 314 is formed over the second dielectric layer 308. First and second trenches 316, 318 are formed in the third dielectric layer 314 and in contact with the first via 310 and the second via 312, respectively. An isolated trench 328 is formed in the third dielectric layer and in contact with the isolated via 326.