Patents by Inventor Ki Duck KIM

Ki Duck KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11157403
    Abstract: There are provided a controller, a memory system having the same, and an operating method thereof. The controller includes: a host interface configured to receive a format request from a host, and output an internal format request including initial logical unit information; and a flash translation layer configured to initialize a map table for storing information on mapping between logical and physical unit numbers according to the initial logical unit information.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Joo Young Lee, Ki Duck Kim, Jea Young Zhang
  • Publication number: 20200183832
    Abstract: There are provided a controller, a memory system having the same, and an operating method thereof. The controller includes: a host interface configured to receive a format request from a host, and output an internal format request including initial logical unit information; and a flash translation layer configured to initialize a map table for storing information on mapping between logical and physical unit numbers according to the initial logical unit information.
    Type: Application
    Filed: July 25, 2019
    Publication date: June 11, 2020
    Inventors: Joo Young LEE, Ki Duck KIM, Jea Young ZHANG
  • Patent number: 10629769
    Abstract: The present invention provides a method of manufacturing a solar cell, the method including: a process of forming a first semiconductor layer on an upper surface of a semiconductor wafer and forming a second semiconductor layer, having a polarity different from a polarity of the first semiconductor layer, on a lower surface of the semiconductor wafer; a process of forming a first transparent conductive layer on an upper surface of the first semiconductor layer to externally expose a portion of the first semiconductor layer and forming a second transparent conductive layer on a lower surface of the second semiconductor layer to externally expose a portion of the second semiconductor layer; and a plasma treatment process on at least one of the first transparent conductive layer and the second transparent conductive layer, wherein the plasma treatment process includes a process of removing the externally exposed portion of the first semiconductor layer and the externally exposed portion of the second semiconduct
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: April 21, 2020
    Assignee: JUSUNG ENGINEERING CO., LTD.
    Inventors: Jeong Ho Seo, Soon Bum Kwon, Ki-Duck Kim, Jong In Kim, Chang Kyun Park, Won Suk Shin, Kyoung Jin Lim, Beop Jong Jin
  • Publication number: 20190180207
    Abstract: A risk management system according to present invention includes a central management server including at least one processor. The processor creates a risk level assessment table based on set likelihood evaluation criteria scores and set consequence evaluation criteria scores, creates a risk factor check list based on information regarding risks and risk factors input by a user, the risks and the risk factors being provided according to tasks, creates an error log based on externally-provided raw data and first user input information, creates a discrepancy log based on externally-provided abnormal event information and second user input information, and creates a risk factor identification and evaluation table based on the risk factor check list, the error log, and the discrepancy log.
    Type: Application
    Filed: May 25, 2018
    Publication date: June 13, 2019
    Inventors: Je Youn DONG, Ki Young MOON, Ki Duck KIM, Soo In LEE
  • Publication number: 20180358506
    Abstract: The present invention provides a method of manufacturing a solar cell, the method including: a process of forming a first semiconductor layer on an upper surface of a semiconductor wafer and forming a second semiconductor layer, having a polarity different from a polarity of the first semiconductor layer, on a lower surface of the semiconductor wafer; a process of forming a first transparent conductive layer on an upper surface of the first semiconductor layer to externally expose a portion of the first semiconductor layer and forming a second transparent conductive layer on a lower surface of the second semiconductor layer to externally expose a portion of the second semiconductor layer; and a plasma treatment process on at least one of the first transparent conductive layer and the second transparent conductive layer, wherein the plasma treatment process includes a process of removing the externally exposed portion of the first semiconductor layer and the externally exposed portion of the second semiconduct
    Type: Application
    Filed: August 21, 2017
    Publication date: December 13, 2018
    Inventors: Jeong Ho SEO, Soon Bum KWON, Ki-Duck KIM, Jong In KIM, Chang Kyun PARK, Won Suk SHIN, Kyoung Jin LIM, Beop Jong JIN
  • Publication number: 20160253257
    Abstract: A data processing system includes a host device suitable for assigning a context identifier to data based on attribute information of the data, and a data storage device suitable for performing a garbage collection operation based on the context identifier.
    Type: Application
    Filed: June 5, 2015
    Publication date: September 1, 2016
    Inventors: Ki Duck KIM, Eu Joon BYUN, Duk Rae LEE, Seung Ho CHOI