Abstract: A semiconductor memory device includes a semiconductor substrate, a cell array region storing data on the substrate, a periphery circuit region on the substrate, the periphery circuit region controlling input and output of the data stored in the cell, a plurality of word-lines and bit-lines on the cell array region, and a plurality of dummy pattern layers on the periphery circuit region.

Abstract: A structure for a semiconductor device includes a plurality of memory cell areas, a multilayer interconnection structure including an interfacial insulating film and connecting the plurality of memory cell areas, the multilayer interconnection structure being insulated and planarized by the interfacial insulating film, and peripheral circuits adjacent to the plurality of memory cell areas, the peripheral circuits intersecting at a portion, wherein the multilayer interconnection structure includes an inflow-preventing layer for preventing an inflow of the interfacial insulating film at the portion where the peripheral circuits intersect.