Abstract: An apparatus is disclosed which includes an ultraviolet laser and at least one reflective mirror having a substrate which is made from beryllium, an aluminum metal matrix, or silicon carbide. The at least one mirror is adapted to reflect a laser beam generated from the ultraviolet laser, which can then be used on a silicon film used in the production of an electronic display. The laser beam can be used to anneal the silicon film, or in a laser lift-off process for separating the silicon film from a temporary substrate upon which the silicon film was mounted.

Abstract: A B-frame processing apparatus including a motion compensation apparatus in the unit of a half pixel for an image decoder adapted to a video appliance such as HDTV. According to the apparatus, motion compensation in the unit of a half pixel is performed in real time with respect to the image having been motion-compensated by frame memories, the half pixel motion-compensated image data is added by an adder to the image data provided from a restoring section, and then the added image data is provided to the frame memories for performing motion. compensation in the unit of a pixel, while the order of the input image is adjusted corresponding to the display order of the final output image.

Abstract: A video motion compensation apparatus comprising an X-read address generation circuit for generating X-read address components in response to a macro block address and an X-motion vector component, a Y-read address generation circuit for generating a Y-read address component in response to a macro slice address and a Y-motion vector component, a write address generation circuit for generating X and Y-write address components in response to the macro slice address and the macro block address, a multiplexing circuit for multiplexing the Y-read address component, the X-read address components and the X and Y-write address components to generate read and write addresses of first and second frame memories, and a data processing circuit for reading video data from a location of one of the first and second frame memories corresponding to the read address from the multiplexing circuit, adding the read video data to inverse discrete cosine transform video data and writing the resultant video data into a location of th

Abstract: A video motion compensation circuit comprising a Y phase variation compensation section for inputting a macro slice address signal and a motion vector Y signal and compensating for a variation in a phase of the motion vector Y signal and a X phase variation compensation section for inputting a macro block address signal and a motion vector X signal and compensating for a variation in a phase of the motion vector X signal. The X phase variation compensation section includes four logic circuits, each having a 2-bit shifter for inputting the macro block address signal of 7 bits and outputting a 9-bit signal, a logic adder for logically combining low order 2 bits of the motion vector X signal of 5 bits to previously add 1 to a LSB of the macro block address signal, and a complement operation unit/shifter for taking a 2's complement of the motion vector X signal of 5 bits and increasing a MSB of the 2's complement-operated signal to output a 9-bit signal.