Abstract: A photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same includes a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines. The first and second photo masks have lower opaque patterns parallel with each other and upper opaque patterns that overlap the lower opaque patterns. In this case, ends of the lower opaque patterns are located on a straight line that crosses the lower opaque patterns. As a result, when upper interconnection lines are formed using the second photo mask, poor photo resist patterns can be prevented from being formed despite the focusing of reflected light.

Abstract: A photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same includes a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines. The first and second photo masks have lower opaque patterns parallel with each other and upper opaque patterns that overlap the lower opaque patterns. In this case, ends of the lower opaque patterns are located on a straight line that crosses the lower opaque patterns. As a result, when upper interconnection lines are formed using the second photo mask, poor photo resist patterns can be prevented from being formed despite the focusing of reflected light.

Abstract: A photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same includes a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines. The first and second photo masks have lower opaque patterns parallel with each other and upper opaque patterns that overlap the lower opaque patterns. In this case, ends of the lower opaque patterns are located on a straight line that crosses the lower opaque patterns. As a result, when upper interconnection lines are formed using the second photo mask, poor photo resist patterns can be prevented from being formed despite the focusing of reflected light.

Abstract: In an embodiment, a method of fabricating a semiconductor device having a hydrogen source layer includes forming an interlayer insulating layer on a semiconductor substrate. A hydrogen source layer is formed on the substrate having the interlayer insulating layer. A thermal annealing process is performed on the substrate having the hydrogen source layer such that hydrogen inside the hydrogen source layer is diffused to a surface of the semiconductor substrate. A conductive pattern is formed on the substrate having the thermally-treated hydrogen source layer. The conductive pattern may be a metal interconnection.

Abstract: A photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same includes a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines. The first and second photo masks have lower opaque patterns parallel with each other and upper opaque patterns that overlap the lower opaque patterns. In this case, ends of the lower opaque patterns are located on a straight line that crosses the lower opaque patterns. As a result, when upper interconnection lines are formed using the second photo mask, poor photo resist patterns can be prevented from being formed despite the focusing of reflected light.

Abstract: A semiconductor device fabrication apparatus is provided for increasing the deposition rate of a film. The apparatus includes a process tube. Process gas injection portions in a slit configuration and waste gas exhaust portions formed as holes are integrated into the interior of the body of the process tube.

Abstract: A semiconductor device fabrication apparatus is provided for increasing the deposition rate of a film. The apparatus includes a process tube. Process gas injection portions in a slit configuration and waste gas exhaust portions formed as holes are integrated into the interior of the body of the process tube.

Abstract: A diffusion system for manufacturing semiconductor devices has an air curtain formed across a furnace opening for preventing the loss of heat energy from inside the furnace. The diffusion system includes the furnace having an opening through which a wafer boat having a plurality of wafers is loaded/unloaded; an air curtain apparatus for spraying a gas across the opening so as to form an air curtain cutting off the atmosphere inside of the furnace from the outside environment; and a controlling unit for controlling the air curtain apparatus by applying on/off signals to the air curtain apparatus. The diffusion system is controlled by the controlling unit so as to form the air curtain at the opening of the furnace while the wafer boat moves in and out of the furnace. After the wafer boat is completely loaded into the furnace, the air curtain is removed.

Abstract: A boat for semiconductor wafers has reduced contact surface area with the wafer, thereby preventing distortion of the wafer during heating. The boat has an upper member; a lower member, a plurality of wafers being loaded between the upper member and the lower member; and a plurality of support members vertically extended between and connecting the upper member to the lower member for supporting the wafers. A plurality of slots are successively and horizontally formed in each of the support members, and the peripheral edge of the wafer is inserted therein, wherein a hemisphere-shaped protrusion is formed inside the slot, and the bottom surface of the wafer contacts and is supported by each hemisphere-shaped protrusion at a single contact point.