Abstract: A display device includes conductive layers on a substrate, a via layer on the conductive layers, a first electrode and a second electrode extending in one direction on the via layer and spaced from each other, a first insulating layer on the first electrode and the second electrode, a plurality of light emitting elements on the first insulating layer, each of the light emitting elements having one end on the first electrode and an other end on the second electrode, and a first connection electrode and a second connection electrode on the first insulating layer, the first connection electrode overlapping the first electrode, and the second connection electrode overlapping the second electrode, wherein the first connection electrode and the second connection electrode are in contact with the conductive layers through contact portions.

Abstract: A semiconductor device may include a substrate including a first cell region, a second cell region, and a dummy region between the first and second cell regions, and conductive patterns included in the first cell region, the second cell region, and the dummy region. A first pattern density, which is defined as a density of the conductive patterns of the first cell region, may be different from a second pattern density, which is defined as a density of the conductive patterns of the second cell region. A third pattern density, which is defined as a density of the conductive patterns of the dummy region, gradually changes in a region between the first cell region and the second cell region. A top surface of the substrate may be inclined at an angle, in the dummy region.

Abstract: A chemical mechanical polishing machine includes a polishing head assembly including a polishing head body and a membrane disposed at a bottom of the polishing head body. The bottom surface of the membrane includes a hydrophobic area and a hydrophilic area.

Abstract: A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.

Abstract: A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.

Abstract: The present invention provides a selective area atomic layer deposition apparatus that deposits an atomic layer thin film on a substrate by supplying a source gas and a purge gas, the apparatus comprising: a reaction chamber; a stage disposed within the reaction chamber, a substrate being disposed on one surface of the stage; a combination nozzle unit disposed above the stage to move relative to the stage; and a gas supply unit that supplies a precursor and an oxidant for forming an atomic layer thin film on the substrate, wherein the combination nozzle unit has a laser core that applies a laser beam to selectively locally heat one surface of the substrate, and the gas supply unit is disposed such that at least a part thereof is adjacent to the laser core, and supplies the precursor and the oxidant to the area on the surface of the substrate that is selectively locally heated by the laser core, wherein the precursor is adsorbed onto the heated area of the substrate, and the oxidant removes ligands of the prec

Abstract: A chemical mechanical polishing machine includes a polishing head assembly including a polishing head body and a membrane disposed at a bottom of the polishing head body. The bottom surface of the membrane includes a hydrophobic area and a hydrophilic area.

Abstract: According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.

Abstract: A chemical mechanical polishing machine includes a polishing head assembly including a polishing head body and a membrane disposed at a bottom of the polishing head body. The bottom surface of the membrane includes a hydrophobic area and a hydrophilic area.

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate, the interlayer insulating layer comprising an opening exposing the substrate, a barrier layer pattern disposed within the opening, and a conductive pattern disposed on the barrier layer pattern, the conductive pattern having an oxidized portion extending out of the opening and a non-oxidized portion within the opening, wherein a width of the conductive pattern is determined by a thickness of the barrier layer pattern.

Abstract: According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate, the interlayer insulating layer comprising an opening exposing the substrate, a barrier layer pattern disposed within the opening, and a conductive pattern disposed on the barrier layer pattern, the conductive pattern having an oxidized portion extending out of the opening and a non-oxidized portion within the opening, wherein a width of the conductive pattern is determined by a thickness of the barrier layer pattern.

Abstract: Provided is a method of fabricating an integrated circuit semiconductor device. The method may include forming a plurality of gate patterns spaced apart from each other on a semiconductor substrate, the plurality of gate patterns including gate electrodes and gate capping patterns. After an interlayer insulating layer is formed to insulate the gate patterns, the interlayer insulating layer and the gate capping patterns may be planarized by etching until top surfaces of the gate electrodes are exposed. Gate metal silicide layers may be selectively formed on the gate electrodes.