Abstract: A capacitor component includes a body including a dielectric layer and first and second internal electrode layers, and external electrodes disposed on the body and connected to the first and second internal electrode layers, respectively. The body includes an active portion in which the first and second internal electrode layers are alternately disposed with the dielectric layer interposed therebetween, a cover portion disposed on an upper portion and a lower portion of the active portion, and a side margin portion disposed on both sides of the active portion opposing each other. When a content of magnesium (Mg) included in the active portion is A1, a content of magnesium (Mg) included in the cover portion is C1, and a content of magnesium (Mg) included in the margin portion is M1, 0<A1<M1?C1 and A1/C1?0.60 are satisfied.

Abstract: Disclosed herein is an apparatus for processing a predictive spatiotemporal query based on synthetic data. The apparatus includes a query-processing unit for analyzing a predictive spatiotemporal query of a user and returning a processing result, a machine-learning unit for training a machine-learning model in response to a request from the query-processing unit and generating synthetic spatiotemporal data based on the machine-learning model, and a data storage unit for storing raw spatiotemporal data and the generated synthetic spatiotemporal data, and the raw spatiotemporal data may be stored in the form of a table including an identifier column and a position column.

Abstract: The present invention relates to a naphthalimide sulfonate derivative, and a photoacid generator and a photoresist composition each comprising same and, more specifically, to a naphthalimide sulfonate derivative compound, and a photoacid generator and a photoresist composition each comprising same, wherein the compound has excellent absorbance for light of i-line (365 nm) wavelength, is greatly easy to prepare into a polymerizable composition due to very high solubility in an organic solvent, has good thermal stability, and shows a favorable acid generation rate.

Abstract: A fuser includes an endless belt; a heat source to heat the endless belt; a pressing roller to press the endless belt to form a heating nip, through which a printing medium is to pass, the pressing roller to rotate the endless belt; a pair of supporting members spaced apart from each other in an axial direction of the endless belt; and a pair of rotational members that are loosely inserted into an inner portion of the endless belt, respectively at two side end portions of the endless belt, the pair of rotational members to be rotatably supported by the pair of supporting members and rotated with the endless belt.

Abstract: A fuser includes an endless belt; a heat source to heat the endless belt; a pressing roller to press the endless belt to form a heating nip, through which a printing medium is to pass, the pressing roller to rotate the endless belt; a pair of supporting members spaced apart from each other in an axial direction of the endless belt; and a pair of rotational members that are loosely inserted into an inner portion of the endless belt, respectively at two side end portions of the endless belt, the pair of rotational members to be rotatably supported by the pair of supporting members and rotated with the endless belt.

Abstract: Provided is a fixing device. The fixing device includes: a fixing belt including a base; a nip forming member arranged inside the fixing belt; and a pressing member arranged outside the fixing belt to face the nip forming member to form a fixing nip. The hardness of the nip forming member is configured with respect to the hardness of the base.

Abstract: Provided is a fixing device. The fixing device includes: a fixing belt including a base; a nip forming member arranged inside the fixing belt; and a pressing member arranged outside the fixing belt to face the nip forming member to form a fixing nip. The hardness of the nip forming member is configured with respect to the hardness of the base.

Abstract: A Decision Feedback Equalizer (DFE) capable of preventing incremental increases of a jitter of a recovered clock and reduction of a voltage margin of decided data due to delay of feedback data. The DFE includes a combiner for combining received data with feedback data and outputting the combined data as equalization data, a decision circuit for deciding recovery data by receiving the equalization data, a feedback loop for supplying the recovery data to the combiner as feedback data and a clock recovery circuit for removing a delay data component from the equalization data through the feedback loop, recovering a clock with respect to the other equalization data except the delay data component and supplying the recovered clock for decision operation of the decision circuit.

Abstract: An offset cancellation circuit includes a sense amplifier configured to receive an input signal and offset voltages and to generate an output signal. A compensation voltage generation section is configured to be inputted with the output signal, and the compensation voltage generation section increases or decreases compensation voltages until the voltage level of the output signal reaches a target voltage level. The voltage level of the compensation voltages is maintained and a control signal is enabled when the voltage level of the output signal reaches the target voltage level. A control loading section is configured to provide the compensation voltages as the offset voltages or maintains the current level of the offset voltages, according to the control signal.

Abstract: An offset cancellation circuit includes a sense amplifier configured to receive an input signal and offset voltages and to generate an output signal. A compensation voltage generation section is configured to be inputted with the output signal, and the compensation voltage generation section increases or decreases compensation voltages until the voltage level of the output signal reaches a target voltage level. The voltage level of the compensation voltages is maintained and a control signal is enabled when the voltage level of the output signal reaches the target voltage level. A control loading section is configured to provide the compensation voltages as the offset voltages or maintains the current level of the offset voltages, according to the control signal.

Abstract: A Decision Feedback Equalizer (DFE) capable of preventing incremental increases of a jitter of a recovered clock and reduction of a voltage margin of decided data due to delay of feedback data. The DFE includes a combiner for combining received data with feedback data and outputting the combined data as equalization data, a decision circuit for deciding recovery data by receiving the equalization data, a feedback loop for supplying the recovery data to the combiner as feedback data and a clock recovery circuit for removing a delay data component from the equalization data through the feedback loop, recovering a clock with respect to the other equalization data except the delay data component and supplying the recovered clock for decision operation of the decision circuit.