Patents by Inventor Ki-Hyun Ko
Ki-Hyun Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8399301Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.Type: GrantFiled: March 4, 2011Date of Patent: March 19, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Joo Park, Ki-Hyun Ko, Young Yun, Soo-Kyung Kim
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Patent number: 8144481Abstract: A memory system includes; a main board having memory bus with a wiring line communicating a signal from a memory controller mounted on the main board, first and second module sockets mounted on the main board and connecting the wiring line to first and second memory modules respectively inserted into the first and second module sockets, where the first memory module includes a first electrode connected to the wiring line and the second memory module includes a second electrode connected to the wiring line, and first and second stub resistors disposed on the main board and arranged as primary dual-branching stub resistors forming a T-branch connection structure between the first and second electrodes and a branching node connected to the wiring line.Type: GrantFiled: December 8, 2009Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Joo Park, Ki-Hyun Ko, Myung-Hee Sung
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Patent number: 8044506Abstract: The invention provides a thermal-emitting memory module, a thermal-emitting module socket, and a computer system comprising the thermal-emitting memory module and the thermal-emitting module socket. An embodiment of the thermal-emitting module includes: a module substrate having electrically-conductive traces; and a semiconductor device disposed on the module substrate and coupled to the electrically-conductive traces, the module substrate including a thermal-emitting portion disposed in proximity of the semiconductor device without directly contacting the semiconductor device.Type: GrantFiled: July 29, 2008Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Young Yun, Soo-Kyung Kim, Kwang-Seop Kim, Ki-Hyun Ko, Sung-Joo Park
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Publication number: 20110163418Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.Type: ApplicationFiled: March 4, 2011Publication date: July 7, 2011Inventors: Sung-Joo Park, Ki-Hyun Ko, Young Yun, Soo-Kyung Kim
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Publication number: 20110165736Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.Type: ApplicationFiled: March 4, 2011Publication date: July 7, 2011Inventors: Sung-Joo Park, Ki-Hyun Ko, Young Yun, Soo-Kyung Kim
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Patent number: 7969761Abstract: In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include at least first and second control signal connectors. The first control signal connector is for a first control signal of a first type, the second control signal connector is for a second control signal of the first type, and the first and second control signal connectors are disposed in different areas of the surface. For example, the first type may be a chip select signal, a clock enable signal, or an on die termination enable signal.Type: GrantFiled: May 5, 2010Date of Patent: June 28, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sungjoo Park, Ki-Hyun Ko, Young Yun, Sookyung Kim
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Patent number: 7919841Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.Type: GrantFiled: January 22, 2008Date of Patent: April 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Joo Park, Ki-Hyun Ko, Young Yun, Soo-Kyung Kim
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Publication number: 20100214814Abstract: In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include at least first and second control signal connectors. The first control signal connector is for a first control signal of a first type, the second control signal connector is for a second control signal of the first type, and the first and second control signal connectors are disposed in different areas of the surface. For example, the first type may be a chip select signal, a clock enable signal, or an on die termination enable signal.Type: ApplicationFiled: May 5, 2010Publication date: August 26, 2010Inventors: Sungjoo Park, Ki-Hyun Ko, Young Yun, Sookyung Kim
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Publication number: 20100177492Abstract: A memory system includes; a main board having memory bus with a wiring line communicating a signal from a memory controller mounted on the main board, first and second module sockets mounted on the main board and connecting the wiring line to first and second memory modules respectively inserted into the first and second module sockets, where the first memory module includes a first electrode connected to the wiring line and the second memory module includes a second electrode connected to the wiring line, and first and second stub resistors disposed on the main board and arranged as primary dual-branching stub resistors forming a T-branch connection structure between the first and second electrodes and a branching node connected to the wiring line.Type: ApplicationFiled: December 8, 2009Publication date: July 15, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Joo PARK, Ki-Hyun KO, Myung-Hee SUNG, Soo-Kyung KIM
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Patent number: 7738277Abstract: In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include at least first and second control signal connectors. The first control signal connector is for a first control signal of a first type, the second control signal connector is for a second control signal of the first type, and the first and second control signal connectors are disposed in different areas of the surface. For example, the first type may be a chip select signal, a clock enable signal, or an on die termination enable signal.Type: GrantFiled: October 3, 2007Date of Patent: June 15, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sungjoo Park, Ki-Hyun Ko, Young Yun, Sookyung Kim
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Publication number: 20090034327Abstract: The invention provides a thermal-emitting memory module, a thermal-emitting module socket, and a computer system comprising the thermal-emitting memory module and the thermal-emitting module socket. An embodiment of the thermal-emitting module includes: a module substrate having electrically-conductive traces; and a semiconductor device disposed on the module substrate and coupled to the electrically-conductive traces, the module substrate including a thermal-emitting component disposed in proximity of the semiconductor device without directly contacting the semiconductor device.Type: ApplicationFiled: July 29, 2008Publication date: February 5, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young YUN, Soo-Kyung KIM, Kwang-Seop KIM, Ki-Hyun KO, Sung-Joo PARK
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Publication number: 20080191338Abstract: In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include at least first and second control signal connectors. The first control signal connector is for a first control signal of a first type, the second control signal connector is for a second control signal of the first type, and the first and second control signal connectors are disposed in different areas of the surface. For example, the first type may be a chip select signal, a clock enable signal, or an on die termination enable signal.Type: ApplicationFiled: October 3, 2007Publication date: August 14, 2008Inventors: Sungjoo Park, Ki Hyun KO, Young YUN, Sookyung KIM
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Publication number: 20080179649Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.Type: ApplicationFiled: January 22, 2008Publication date: July 31, 2008Inventors: Sung-Joo Park, Ki-Hyun Ko, Young Yun, Soo-Kyung Kim
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Patent number: 7390973Abstract: The pesent invention discloses a memory module and a signal line arrangement method thereof. The memory module includes memory chips mounted on both sidees in a mirror form; and a printed circuit board (PCB) having same signal applying contact pads arranged on both sodes which same signal applying balls of the memory chips contact in the mirror form, wherein a via is formed at a location close to the same signal applying contact pad of one side among the same signal applying contact pads arranged on both sides in the mirror form, the via connecting the other side to the signal line of one side, and a signal transmitted from the other side is connected to a contact junction, the contact junction is connected to the same signal applying contact pad of the other side, the contact junction is connected to the via of the other side, and the via of one side is connected to the same signal applying contact pad of one side.Type: GrantFiled: February 17, 2006Date of Patent: June 24, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Chil-Nam Yoon, Kwang-Seop Kim, Do-Hyung Kim, Jae-Jun Lee, Ki-Hyun Ko
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Patent number: 7348219Abstract: A memory module and a method of mounting memory devices on a PCB to form the memory module substantially reduce unnecessary routing space and improve signal attenuation characteristics. In the method of mounting and sequentially connecting at least two memory devices on a printed circuit board (PCB) having an axis of elongation to form a memory module, at least one of the memory devices is mounted on at least one face of the PCB so that a base line along an longitudinal axis of the at least one memory device lies at an acute angle with respect to the axis of elongation of the PCB.Type: GrantFiled: December 12, 2005Date of Patent: March 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Do-Hyung Kim, Chang-Woo Koo, Jung-Joon Lee, Ki-Hyun Ko
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Publication number: 20070164448Abstract: Provided are a semiconductor chip package with attached electronic devices, and an integrated circuit module having the same. The semiconductor chip packages may include a supporting substrate, input/output bonding pads arranged on a first plane of the supporting substrate, and device bonding pads arranged on the edges of the first plane or portions of the first plane adjacent to the edges. Accordingly, the mount area of a printed circuit board may be reduced, efficient routing may be possible, and the occurrence of package cracks may be reduced and/or prevented.Type: ApplicationFiled: August 17, 2006Publication date: July 19, 2007Inventors: Kyoung-Sun Kim, Ki-Hyun Ko, Byoung-Ha Oh
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Publication number: 20060207788Abstract: In a memory module and a signal line arrangement method thereof, the memory module comprises: memory chips mounted on both sides of the module in a mirrored configuration; and a printed circuit board (PCB) having same signal applying contact pads arranged on both sides in contact with same signal applying balls of the memory chips in the mirrored configuration, the PCB including a via at a location proximal to the same signal applying contact pad of one side of the PCB among the same signal applying contact pads arranged on both sides in the mirrored configuration, the via connecting an other side of the PCB to the one side of the PCB, and a contact junction connected to the same signal applying contact pad of the other side of the PCB, the contact junction being connected to the via of the other side of the PCB, and the via of the one side of the PCB being connected to the same signal applying contact pad of the one side of the PCB, the contact junction connected to a signal terminal from the other side of tType: ApplicationFiled: February 17, 2006Publication date: September 21, 2006Inventors: Chil-Nam Yoon, Kwang-Seop Kim, Do-Hyung Kim, Jae-Jun Lee, Ki-Hyun Ko
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Publication number: 20060125071Abstract: A memory module and a method of mounting memory devices on a PCB to form the memory module substantially reduce unnecessary routing space and improve signal attenuation characteristics. In the method of mounting and sequentially connecting at least two memory devices on a printed circuit board(PCB) having an axis of elongation to form a memory module, at least one of the memory devices is mounted on at least one face of the PCB so that a base line along an longitudinal axis of the at least one memory device lies at an acute angle with respect to the axis of elongation of the PCB.Type: ApplicationFiled: December 12, 2005Publication date: June 15, 2006Inventors: Do-Hyung Kim, Chang-Woo Koo, Jung-Joon Lee, Ki-Hyun Ko
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Patent number: 6891729Abstract: A memory module preferably includes a printed circuit board (PCB) panel having multiple memory chip pad groups arranged on both sides thereof. Each memory chip pad group preferably includes multiple pads that correspond to lead lines of multiple memory chips arranged on the PCB panel. Connectors are preferably formed along an edge of the PCB panel to electrically connect the memory chip pad groups to an external device. Multiple damping chip pad groups preferably include built-in damping chips. One or more of the damping chip pad groups are preferably arranged adjacent to a lateral edge of one or more of the memory chips. The damping chip pad groups can electrically connect the connectors to the memory chip pad groups and dampen the signal noises.Type: GrantFiled: July 16, 2002Date of Patent: May 10, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Hyun Ko, Kwang-Seop Kim
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Patent number: D1017611Type: GrantFiled: June 26, 2023Date of Patent: March 12, 2024Assignee: Samsung Display Co., Ltd.Inventors: Ho Jung Lee, Kyung Hyun Ko, Yong Woo Koo, Jun Il Kwon, Pablo Kim, Young-Su Kim, Jun Woo Kim, Hoon Kim, Hye Suk An, Hyun Joo Lee, Ki Ho Lim