Patents by Inventor Ki-Hyun Ko

Ki-Hyun Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8399301
    Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: March 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Joo Park, Ki-Hyun Ko, Young Yun, Soo-Kyung Kim
  • Patent number: 8144481
    Abstract: A memory system includes; a main board having memory bus with a wiring line communicating a signal from a memory controller mounted on the main board, first and second module sockets mounted on the main board and connecting the wiring line to first and second memory modules respectively inserted into the first and second module sockets, where the first memory module includes a first electrode connected to the wiring line and the second memory module includes a second electrode connected to the wiring line, and first and second stub resistors disposed on the main board and arranged as primary dual-branching stub resistors forming a T-branch connection structure between the first and second electrodes and a branching node connected to the wiring line.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: March 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Joo Park, Ki-Hyun Ko, Myung-Hee Sung
  • Patent number: 8044506
    Abstract: The invention provides a thermal-emitting memory module, a thermal-emitting module socket, and a computer system comprising the thermal-emitting memory module and the thermal-emitting module socket. An embodiment of the thermal-emitting module includes: a module substrate having electrically-conductive traces; and a semiconductor device disposed on the module substrate and coupled to the electrically-conductive traces, the module substrate including a thermal-emitting portion disposed in proximity of the semiconductor device without directly contacting the semiconductor device.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: October 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Yun, Soo-Kyung Kim, Kwang-Seop Kim, Ki-Hyun Ko, Sung-Joo Park
  • Publication number: 20110163418
    Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.
    Type: Application
    Filed: March 4, 2011
    Publication date: July 7, 2011
    Inventors: Sung-Joo Park, Ki-Hyun Ko, Young Yun, Soo-Kyung Kim
  • Publication number: 20110165736
    Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.
    Type: Application
    Filed: March 4, 2011
    Publication date: July 7, 2011
    Inventors: Sung-Joo Park, Ki-Hyun Ko, Young Yun, Soo-Kyung Kim
  • Patent number: 7969761
    Abstract: In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include at least first and second control signal connectors. The first control signal connector is for a first control signal of a first type, the second control signal connector is for a second control signal of the first type, and the first and second control signal connectors are disposed in different areas of the surface. For example, the first type may be a chip select signal, a clock enable signal, or an on die termination enable signal.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: June 28, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungjoo Park, Ki-Hyun Ko, Young Yun, Sookyung Kim
  • Patent number: 7919841
    Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: April 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Joo Park, Ki-Hyun Ko, Young Yun, Soo-Kyung Kim
  • Publication number: 20100214814
    Abstract: In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include at least first and second control signal connectors. The first control signal connector is for a first control signal of a first type, the second control signal connector is for a second control signal of the first type, and the first and second control signal connectors are disposed in different areas of the surface. For example, the first type may be a chip select signal, a clock enable signal, or an on die termination enable signal.
    Type: Application
    Filed: May 5, 2010
    Publication date: August 26, 2010
    Inventors: Sungjoo Park, Ki-Hyun Ko, Young Yun, Sookyung Kim
  • Publication number: 20100177492
    Abstract: A memory system includes; a main board having memory bus with a wiring line communicating a signal from a memory controller mounted on the main board, first and second module sockets mounted on the main board and connecting the wiring line to first and second memory modules respectively inserted into the first and second module sockets, where the first memory module includes a first electrode connected to the wiring line and the second memory module includes a second electrode connected to the wiring line, and first and second stub resistors disposed on the main board and arranged as primary dual-branching stub resistors forming a T-branch connection structure between the first and second electrodes and a branching node connected to the wiring line.
    Type: Application
    Filed: December 8, 2009
    Publication date: July 15, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Joo PARK, Ki-Hyun KO, Myung-Hee SUNG, Soo-Kyung KIM
  • Patent number: 7738277
    Abstract: In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include at least first and second control signal connectors. The first control signal connector is for a first control signal of a first type, the second control signal connector is for a second control signal of the first type, and the first and second control signal connectors are disposed in different areas of the surface. For example, the first type may be a chip select signal, a clock enable signal, or an on die termination enable signal.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: June 15, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungjoo Park, Ki-Hyun Ko, Young Yun, Sookyung Kim
  • Publication number: 20090034327
    Abstract: The invention provides a thermal-emitting memory module, a thermal-emitting module socket, and a computer system comprising the thermal-emitting memory module and the thermal-emitting module socket. An embodiment of the thermal-emitting module includes: a module substrate having electrically-conductive traces; and a semiconductor device disposed on the module substrate and coupled to the electrically-conductive traces, the module substrate including a thermal-emitting component disposed in proximity of the semiconductor device without directly contacting the semiconductor device.
    Type: Application
    Filed: July 29, 2008
    Publication date: February 5, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young YUN, Soo-Kyung KIM, Kwang-Seop KIM, Ki-Hyun KO, Sung-Joo PARK
  • Publication number: 20080191338
    Abstract: In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include at least first and second control signal connectors. The first control signal connector is for a first control signal of a first type, the second control signal connector is for a second control signal of the first type, and the first and second control signal connectors are disposed in different areas of the surface. For example, the first type may be a chip select signal, a clock enable signal, or an on die termination enable signal.
    Type: Application
    Filed: October 3, 2007
    Publication date: August 14, 2008
    Inventors: Sungjoo Park, Ki Hyun KO, Young YUN, Sookyung KIM
  • Publication number: 20080179649
    Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.
    Type: Application
    Filed: January 22, 2008
    Publication date: July 31, 2008
    Inventors: Sung-Joo Park, Ki-Hyun Ko, Young Yun, Soo-Kyung Kim
  • Patent number: 7390973
    Abstract: The pesent invention discloses a memory module and a signal line arrangement method thereof. The memory module includes memory chips mounted on both sidees in a mirror form; and a printed circuit board (PCB) having same signal applying contact pads arranged on both sodes which same signal applying balls of the memory chips contact in the mirror form, wherein a via is formed at a location close to the same signal applying contact pad of one side among the same signal applying contact pads arranged on both sides in the mirror form, the via connecting the other side to the signal line of one side, and a signal transmitted from the other side is connected to a contact junction, the contact junction is connected to the same signal applying contact pad of the other side, the contact junction is connected to the via of the other side, and the via of one side is connected to the same signal applying contact pad of one side.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: June 24, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chil-Nam Yoon, Kwang-Seop Kim, Do-Hyung Kim, Jae-Jun Lee, Ki-Hyun Ko
  • Patent number: 7348219
    Abstract: A memory module and a method of mounting memory devices on a PCB to form the memory module substantially reduce unnecessary routing space and improve signal attenuation characteristics. In the method of mounting and sequentially connecting at least two memory devices on a printed circuit board (PCB) having an axis of elongation to form a memory module, at least one of the memory devices is mounted on at least one face of the PCB so that a base line along an longitudinal axis of the at least one memory device lies at an acute angle with respect to the axis of elongation of the PCB.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: March 25, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Hyung Kim, Chang-Woo Koo, Jung-Joon Lee, Ki-Hyun Ko
  • Publication number: 20070164448
    Abstract: Provided are a semiconductor chip package with attached electronic devices, and an integrated circuit module having the same. The semiconductor chip packages may include a supporting substrate, input/output bonding pads arranged on a first plane of the supporting substrate, and device bonding pads arranged on the edges of the first plane or portions of the first plane adjacent to the edges. Accordingly, the mount area of a printed circuit board may be reduced, efficient routing may be possible, and the occurrence of package cracks may be reduced and/or prevented.
    Type: Application
    Filed: August 17, 2006
    Publication date: July 19, 2007
    Inventors: Kyoung-Sun Kim, Ki-Hyun Ko, Byoung-Ha Oh
  • Publication number: 20060207788
    Abstract: In a memory module and a signal line arrangement method thereof, the memory module comprises: memory chips mounted on both sides of the module in a mirrored configuration; and a printed circuit board (PCB) having same signal applying contact pads arranged on both sides in contact with same signal applying balls of the memory chips in the mirrored configuration, the PCB including a via at a location proximal to the same signal applying contact pad of one side of the PCB among the same signal applying contact pads arranged on both sides in the mirrored configuration, the via connecting an other side of the PCB to the one side of the PCB, and a contact junction connected to the same signal applying contact pad of the other side of the PCB, the contact junction being connected to the via of the other side of the PCB, and the via of the one side of the PCB being connected to the same signal applying contact pad of the one side of the PCB, the contact junction connected to a signal terminal from the other side of t
    Type: Application
    Filed: February 17, 2006
    Publication date: September 21, 2006
    Inventors: Chil-Nam Yoon, Kwang-Seop Kim, Do-Hyung Kim, Jae-Jun Lee, Ki-Hyun Ko
  • Publication number: 20060125071
    Abstract: A memory module and a method of mounting memory devices on a PCB to form the memory module substantially reduce unnecessary routing space and improve signal attenuation characteristics. In the method of mounting and sequentially connecting at least two memory devices on a printed circuit board(PCB) having an axis of elongation to form a memory module, at least one of the memory devices is mounted on at least one face of the PCB so that a base line along an longitudinal axis of the at least one memory device lies at an acute angle with respect to the axis of elongation of the PCB.
    Type: Application
    Filed: December 12, 2005
    Publication date: June 15, 2006
    Inventors: Do-Hyung Kim, Chang-Woo Koo, Jung-Joon Lee, Ki-Hyun Ko
  • Patent number: 6891729
    Abstract: A memory module preferably includes a printed circuit board (PCB) panel having multiple memory chip pad groups arranged on both sides thereof. Each memory chip pad group preferably includes multiple pads that correspond to lead lines of multiple memory chips arranged on the PCB panel. Connectors are preferably formed along an edge of the PCB panel to electrically connect the memory chip pad groups to an external device. Multiple damping chip pad groups preferably include built-in damping chips. One or more of the damping chip pad groups are preferably arranged adjacent to a lateral edge of one or more of the memory chips. The damping chip pad groups can electrically connect the connectors to the memory chip pad groups and dampen the signal noises.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: May 10, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Hyun Ko, Kwang-Seop Kim
  • Patent number: D1017611
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: March 12, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ho Jung Lee, Kyung Hyun Ko, Yong Woo Koo, Jun Il Kwon, Pablo Kim, Young-Su Kim, Jun Woo Kim, Hoon Kim, Hye Suk An, Hyun Joo Lee, Ki Ho Lim