Abstract: A display device includes a display panel, a variable gate clock generator and a gate driver. The display panel includes a plurality of pixels coupled to a plurality of data lines and a plurality of gate lines, respectively. The variable gate clock generator generates a first variable gate clock signal and a second variable gate clock signal having respective duty ratios that are varied depending on a brightness of a frame image. The gate driver generates a plurality of gate driving signals for driving the gate lines in response to the first and second variable gate clock signals.

Abstract: A method of driving a display panel includes steps of generating a plurality of load signals, of which at least one load signal has a different timing from the rest of the load signals, generating data voltages synchronized to low periods of the load signals and outputting the data voltages to data lines. Accordingly, the data voltages synchronized to each of the load signals can be outputted to each of the data lines. A color coordinate problem occurring when applying a RGBW type may be solved by setting a charging time of a white sub-pixel different from the rest of the sub-pixels. Thus, display quality of a display apparatus including the display panel may be improved.

Abstract: A display apparatus comprises a display panel including a plurality of data lines and a plurality of gate lines, a data driver circuit configured to convert image data to a grayscale voltage and to output the grayscale voltage to a data line, a voltage generator configured to provide the data driver circuit to a driving voltage, and a heat blocking circuit configured to compare a load current voltage with a reference voltage and to output a control signal for controlling the data driver circuit, the load current voltage being proportionate to a load current flowing toward the data driver circuit.

Abstract: A gate driving module includes a gate driver and a gate signal generator. The gate driver generates a vertical start signal, a plurality of gate clock signals and a plurality of inverse gate clock signals based on a vertical start control signal, a plurality of gate clock control signals, a gate on voltage, a first gate off voltage and a second gate off voltage. The number of the gate clock signals is P. The number of the inverse gate clock signals is P. The number of the gate clock control signals is P. P is a positive integer equal to or greater than two. The gate signal generator generates a gate signal based on the vertical start signal, the gate clock signals and the inverse gate clock signals.

Abstract: A method of driving a display panel includes providing at least one gate line among a plurality of gate lines disposed in the display panel with a gate signal of a gate-on level during a vertical blanking period of a frame period and providing a data line disposed in the display panel with data voltages of a first polarity and a second polarity opposite to the first polarity during the vertical blanking period.

Abstract: A display device includes: a plurality of pixels; a scan driver configured to apply a scan signal to a plurality of scan lines connected to the plurality of pixels; a data driver configured to apply a gray voltage to a plurality of data lines connected to the plurality of pixels; a signal controller configured to transmit a scan control signal for controlling operating of the scan driver to the scan driver, and configured to transmit a data control signal for controlling operating of the data driver to the data driver; a power supply configured to supply a power voltage for generation of the scan signal to the scan driver; and a short detector configured to detect a voltage level of the power voltage and generate an enable signal in response to the detection.

Abstract: A method of driving a display panel includes comparing a previous frame data and a present frame data, outputting an inversion control signal of the present frame based on a result of the comparing the previous frame data and the present frame data, generating a positive pixel voltage and a negative pixel voltage based on the inversion control signal and displaying an image based on the positive pixel voltage and the negative pixel voltage.

Abstract: A method of driving a display panel, the method including outputting video data to a display panel during an N-th (N is a natural number) frame, outputting video data to the display panel during an (N+1)-th frame, comparing polarities of video data of the N-th frame and corresponding polarities of video data of the (N+1)-th frame, and controlling polarities of video data of an (N+2)-th frame, according to the result of the comparison.

Abstract: A display apparatus includes a display panel including a plurality of data lines arranged in a first direction, where the data line extends substantially in a second direction, and a plurality of pixels electrically connected to the data lines, and a data driver configured to output a first data voltage and a second data voltage to the data lines and configured to control the number of the data lines which receives the first data voltage and the number of the data lines which receive the second data voltage, where the first data voltage has a positive polarity during a first frame and a negative polarity during a second frame, and the second data voltage has the negative polarity during the first frame and the positive polarity during the second frame.

Abstract: A method of reducing a time for switching a gate line driving signal of display device having plural gate lines from a level that is less than a full gate-on level to the gate-on level is disclosed. The method may include: during a gate line pre-charging period of a respective gate line, causing the gate line driving signal to be at the full gate-on level; during a corresponding gate line main-charging period that follows the pre-charging period, causing the gate line driving signal of to be at the full gate-on level; and during an interposed period that is interposed between the gate line pre-charging period and its corresponding gate line main-charging period, causing the gate line driving signal to be at an intermediate level that is between the full gate-on level and an opposed gate-off level.

Abstract: A circuit includes a reference signal generating part configured to generate a plurality of reference signals having levels different from each other, a comparing part configured to compare a ripple signal with the reference signals to determine a level of the ripple signal, a compensating signal generating part configured to generate a compensation ripple signal corresponding to the level of the ripple signal, where the compensation ripple signal has a phase opposite to the ripple signal, and a push-pull circuit configured to stabilize the compensation ripple signal.

Abstract: A method of driving a display panel is provided. The method includes displaying a first image on at least one odd-numbered horizontal line of the display panel along a first direction and a second direction during a first period of a frame period and displaying a second image on at least one even-numbered horizontal line of the display panel along the first direction and second direction during a second period of the frame period.

Abstract: A method of driving a display panel includes: selectively providing a resistance using resistor parts in response to address signals, where the resistor parts have resistances, respectively; and outputting common voltages to the display panel based on the selectively provided resistance.

Abstract: A display panel driving apparatus is disclosed. In one aspect the apparatus includes a gate driving part and a data driving part. The gate driving part is configured to increase a gate signal applied to a gate line of a display panel from an OFF voltage to a ON voltage, in response to an activation of a gate clock signal. It is also configured to decrease the gate signal from the ON voltage to a kickback compensation voltage between the OFF voltage and the ON voltage through a plurality of steps in response to an activation of a kickback compensation signal. The data driving part is configured to apply a data signal to a data line of the display panel. Therefore, a data-charging rate may be increased, and thus a display quality of the display apparatus may be increased.

Abstract: A method of driving a display panel includes providing at least one gate line among a plurality of gate lines disposed in the display panel with a gate signal of a gate-on level during a vertical blanking period of a frame period and providing a data line disposed in the display panel with data voltages of a first polarity and a second polarity opposite to the first polarity during the vertical blanking period.

Abstract: A gate driving module includes a gate driver and a gate signal generator. The gate driver generates a vertical start signal, a plurality of gate clock signals and a plurality of inverse gate clock signals based on a vertical start control signal, a plurality of gate clock control signals, a gate on voltage, a first gate off voltage and a second gate off voltage. The number of the gate clock signals is P. The number of the inverse gate clock signals is P. The number of the gate clock control signals is P. P is a positive integer equal to or greater than two. The gate signal generator generates a gate signal based on the vertical start signal, the gate clock signals and the inverse gate clock signals.

Abstract: A driving circuit including a timing control part, a driving voltage generating part, a voltage modifying part, and a slope control part. The voltage modifying part is configured to modify the gate-on voltage to a swing-on signal based on the kickback control signal, the swing-on signal including a slicing part, the slicing part including a falling portion during which a level of the swing-on signal falls from the first high level to a second high level lower than the first high level, and a rising portion during which the level of the swing-on signal rises from the second high level to the first high level. The slope control part is configured to decrease a slew rate of the rising portion in the swing-on signal and to output the swing-on signal decreased the slew rate of the rising portion as a gate-on signal.

Abstract: A method quickly resuming a downlink service in a hard handover in a cellular mobile communication system. To provide the fast downlink service to an MS during a hard handover from an OBS to an NBS, the NBS receives handover user information from the OBS, and generates an MS temporary ID using the handover user information to identify the MS. If user data is generated for the MS before a connection is established for traffic transmission between the MS and the NBS, the NBS transmits the user data to the MS on an HCCH using the MS temporary ID.

Abstract: An HARQ method for guaranteeing a QoS in a wireless communication system is provided. In a transmitting apparatus using a HARQ for transmitting packet data in a wireless communication system, a retransmission controller determines the size of redundancy information for correcting transmission errors in packet data, and a transmitter transmits the redundancy information of the determined size upon request for a retransmission of the packet data. Transmission of redundancy information of a variable size at each retransmission satisfies the QoS required for each user, maximizes a data throughput, and allows for the efficient reception of an ACK or a NACK for the redundancy information.

Abstract: An HARQ method for guaranteeing a QoS in a wireless communication system is provided. In a transmitting apparatus using a HARQ for transmitting packet data in a wireless communication system, a retransmission controller determines the size of redundancy information for correcting transmission errors in packet data, and a transmitter transmits the redundancy information of the determined size upon request for a retransmission of the packet data. Transmission of redundancy information of a variable size at each retransmission satisfies the QoS required for each user, maximizes a data throughput, and allows for the efficient reception of an ACK or a NACK for the redundancy information.