Patents by Inventor Ki-Hyung Ko
Ki-Hyung Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230068364Abstract: A semiconductor device includes an active pattern provided on a substrate, a source/drain pattern provided on the active pattern, a channel pattern configured to be connected to the source/drain pattern, a gate electrode configured to be extended in a first direction and to cross the channel pattern, and a first spacer provided on a side surface of the gate electrode. The first spacer includes a fence portion provided on a side surface of the active pattern and below the source/drain pattern. The source/drain pattern includes a body portion and a neck portion between the body portion and the active pattern. The body portion includes a crystalline surface configured to be slantingly extended from the neck portion. The crystalline surface is configured to be spaced apart from an uppermost portion of the fence portion.Type: ApplicationFiled: April 12, 2022Publication date: March 2, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyungin Choi, Dongmyoung Kim, Haejun Yu, Ki-Hyung Ko, Jiho Yoo, Soonwook Jung
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Patent number: 10734380Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.Type: GrantFiled: October 12, 2018Date of Patent: August 4, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
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Patent number: 10714472Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.Type: GrantFiled: August 14, 2017Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kee Sang Kwon, Boun Yoon, Sangjine Park, Myunggeun Song, Ki-Hyung Ko, Jiwon Yun
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Publication number: 20190043860Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.Type: ApplicationFiled: October 12, 2018Publication date: February 7, 2019Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
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Patent number: 10128236Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.Type: GrantFiled: January 27, 2016Date of Patent: November 13, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
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Patent number: 10115797Abstract: In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.Type: GrantFiled: March 3, 2016Date of Patent: October 30, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-yeol Song, Wan-don Kim, Sang-Jin Hyun, Jin-wook Lee, Kee-sang Kwon, Ki-hyung Ko, Sung-woo Myung
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Publication number: 20180197861Abstract: A first conductivity type finFET device can include first embedded sources/drains of a first material that have a first etch rate. The first embedded sources/drains can each include an upper surface having a recessed portion and an outer raised portion relative to the recessed portion. A second conductivity type finFET device can include second embedded sources/drains of a second material that have a second etch rate than is greater that the first etch rate. The second embedded sources/drains can each include an upper surface that is at a different level than the outer raised portions of the first conductivity type finFET device.Type: ApplicationFiled: March 9, 2018Publication date: July 12, 2018Inventors: Sang Jine Park, KI HYUNG KO, KEE SANG KWON, JAE JIK BAEK, BO UN YOON, YONG SUN KO
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Publication number: 20170345822Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.Type: ApplicationFiled: August 14, 2017Publication date: November 30, 2017Inventors: Kee Sang Kwon, Boun YOON, Sangjine PARK, Myunggeun SONG, Ki-Hyung KO, Jiwon YUN
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Patent number: 9748234Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.Type: GrantFiled: August 14, 2015Date of Patent: August 29, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kee Sang Kwon, Boun Yoon, Sangjine Park, Myunggeun Song, Ki-Hyung Ko, Jiwon Yun
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Publication number: 20160308012Abstract: In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.Type: ApplicationFiled: March 3, 2016Publication date: October 20, 2016Inventors: Jae-yeol Song, Wan-don Kim, Sang-jin Hyun, Jin-wook Lee, Kee-sang Kwon, Ki-hyung Ko, Sung-woo Myung
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Publication number: 20160284699Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.Type: ApplicationFiled: January 27, 2016Publication date: September 29, 2016Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
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Publication number: 20160064378Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.Type: ApplicationFiled: August 14, 2015Publication date: March 3, 2016Inventors: Kee Sang KWON, Boun Yoon, Sangjine Park, Myunggeun Song, Ki-Hyung Ko, Jiwon Yun
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Patent number: 8859371Abstract: Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.Type: GrantFiled: March 12, 2013Date of Patent: October 14, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Geun Song, Ki-Hyung Ko, Hayoung Jeon, Boun Yoon, Jeongnam Han
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Patent number: 8617991Abstract: A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.Type: GrantFiled: June 19, 2012Date of Patent: December 31, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Chan Lee, Yoo-Jung Lee, Ki-Hyung Ko, Dae-Young Kwak, Seung-Jae Lee, Jae-Sung Hur, Sang-Bom Kang, Cheol Kim, Bo-Un Yoon
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Publication number: 20130244414Abstract: Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.Type: ApplicationFiled: March 12, 2013Publication date: September 19, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung Geun Song, Ki-Hyung Ko, Hayoung Jeon, Boun Yoon, Jeongnam Han
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Publication number: 20130012021Abstract: A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.Type: ApplicationFiled: June 19, 2012Publication date: January 10, 2013Inventors: Jung-Chan LEE, Yoo-Jung LEE, Ki-Hyung KO, Dae-Young KWAK, Seung-Jae LEE, Jae-Sung HUR, Sang-Bom KANG, Cheol KIM, Bo-Un YOON
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Patent number: 8168509Abstract: In an etching method, a thin layer is formed on a first surface of a first substrate doped with first impurities having a first doping concentration. The thin layer is doped with second impurities having a second doping concentration lower than the first doping concentration. A second substrate is formed on the thin layer. A second surface of the first substrate is polished. The polished first substrate is cleaned using a cleaning solution including ammonia and deionized water. The cleaned first substrate is etched to expose the thin layer.Type: GrantFiled: December 3, 2010Date of Patent: May 1, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Hyung Ko, Byoung-Moon Yoon, Won-Jun Lee, Joon-Sang Park, Jun-Youl Yang, Seung-Ho Park, Myung-Jung Pyo
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Publication number: 20110136290Abstract: In an etching method, a thin layer is formed on a first surface of a first substrate doped with first impurities having a first doping concentration. The thin layer is doped with second impurities having a second doping concentration lower than the first doping concentration. A second substrate is formed on the thin layer. A second surface of the first substrate is polished. The polished first substrate is cleaned using a cleaning solution including ammonia and deionized water. The cleaned first substrate is etched to expose the thin layer.Type: ApplicationFiled: December 3, 2010Publication date: June 9, 2011Inventors: Ki-Hyung KO, Byoung-Moon Yoon, Won-Jun Lee, Joon-Sang Park, Jun-Youl Yang, Seung-Ho Park, Myung-Jung Pyo
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Publication number: 20100178754Abstract: A method of manufacturing a complementary metal-oxide semiconductor (CMOS) transistor includes: forming a semiconductor layer in which an n-MOS transistor region and a p-MOS transistor region are defined; forming an insulation layer on the semiconductor layer; forming a conductive layer on the insulation layer; forming a mask pattern exposing the n-MOS transistor region, on the conductive layer; generating a damage region in an upper portion of the conductive layer by implanting impurities in the conductive layer of the n-MOS transistor region using the mask pattern as a mask; removing the mask pattern; removing the damage region; and patterning the conductive layer to form an n-MOS transistor gate and a p-MOS transistor gate. Accordingly, gate thinning and formation of a step between the n-MOS transistor region gate and the p-MOS transistor region gate can be prevented.Type: ApplicationFiled: June 5, 2009Publication date: July 15, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-youl Yang, Byoung-moon Yoon, Cheol-woo Park, Won-jun Lee, Ki-hyung Ko