Patents by Inventor Ki-hyung NAM
Ki-hyung NAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11856752Abstract: A semiconductor device includes an active region in a substrate, an isolation film defining the active region in the substrate, a gate trench extending across the active region and the isolation film and including a first trench in the active region and a second trench in the isolation film, a gate electrode including a main gate electrode and a pass gate electrode, the main gate electrode filling a lower part of the first trench, and the pass gate electrode filling a lower part of the second trench, a support structure on the pass gate electrode, the support structure filling an upper part of the second trench, a gate insulating film interposed between the isolation film and the pass gate electrode and between the support structure and the pass gate electrode.Type: GrantFiled: May 3, 2021Date of Patent: December 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Ki-Hyung Nam
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Publication number: 20210288053Abstract: A semiconductor device includes an active region in a substrate, an isolation film defining the active region in the substrate, a gate trench extending across the active region and the isolation film and including a first trench in the active region and a second trench in the isolation film, a gate electrode including a main gate electrode and a pass gate electrode, the main gate electrode filling a lower part of the first trench, and the pass gate electrode filling a lower part of the second trench, a support structure on the pass gate electrode, the support structure filling an upper part of the second trench, a gate insulating film interposed between the isolation film and the pass gate electrode and between the support structure and the pass gate electrode.Type: ApplicationFiled: May 3, 2021Publication date: September 16, 2021Inventor: Ki-Hyung NAM
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Patent number: 11004854Abstract: A semiconductor device includes an active region in a substrate, an isolation film defining the active region in the substrate, a gate trench extending across the active region and the isolation film and including a first trench in the active region and a second trench in the isolation film, a gate electrode including a main gate electrode and a pass gate electrode, the main gate electrode filling a lower part of the first trench, and the pass gate electrode filling a lower part of the second trench, a support structure on the pass gate electrode, the support structure filling an upper part of the second trench, a gate insulating film interposed between the isolation film and the pass gate electrode and between the support structure and the pass gate electrode.Type: GrantFiled: May 28, 2019Date of Patent: May 11, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Ki-Hyung Nam
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Patent number: 10991807Abstract: A semiconductor device includes gate trench, an upper gate insulating layer on an inner surface of an upper region of the gate trench, a lower gate insulating layer on an inner surface and a lower surface of a lower region of the gate trench and connected to the upper gate insulating layer, a first gate barrier layer on an inner side of the lower gate insulating layer, a gate electrode on an inner side of the first gate barrier layer and configured to fill the lower region of the gate trench, and a gate buried portion on the gate electrode. A diameter of an inner circumference of an upper end of the lower gate insulating layer is greater than a diameter of an inner circumference of a lower end of the upper gate insulating layer.Type: GrantFiled: March 13, 2019Date of Patent: April 27, 2021Assignee: Samsung Electronics Co., Ltd.Inventor: Ki Hyung Nam
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Patent number: 10714565Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.Type: GrantFiled: October 4, 2019Date of Patent: July 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-hyung Nam, Bong-Soo Kim, Yoosang Hwang
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Publication number: 20200161305Abstract: A semiconductor device includes an active region in a substrate, an isolation film defining the active region in the substrate, a gate trench extending across the active region and the isolation film and including a first trench in the active region and a second trench in the isolation film, a gate electrode including a main gate electrode and a pass gate electrode, the main gate electrode filling a lower part of the first trench, and the pass gate electrode filling a lower part of the second trench, a support structure on the pass gate electrode, the support structure filling an upper part of the second trench, a gate insulating film interposed between the isolation film and the pass gate electrode and between the support structure and the pass gate electrode.Type: ApplicationFiled: May 28, 2019Publication date: May 21, 2020Inventor: Ki-Hyung NAM
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Publication number: 20200091303Abstract: A semiconductor device includes gate trench, an upper gate insulating layer on an inner surface of an upper region of the gate trench, a lower gate insulating layer on an inner surface and a lower surface of a lower region of the gate trench and connected to the upper gate insulating layer, a first gate barrier layer on an inner side of the lower gate insulating layer, a gate electrode on an inner side of the first gate barrier layer and configured to fill the lower region of the gate trench, and a gate buried portion on the gate electrode. A diameter of an inner circumference of an upper end of the lower gate insulating layer is greater than a diameter of an inner circumference of a lower end of the upper gate insulating layer.Type: ApplicationFiled: March 13, 2019Publication date: March 19, 2020Applicant: Samsung Electronics Co., Ltd.Inventor: Ki Hyung Nam
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Publication number: 20200035781Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.Type: ApplicationFiled: October 4, 2019Publication date: January 30, 2020Inventors: Ki-hyung NAM, Bong-Soo KIM, Yoosang HWANG
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Patent number: 10483346Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.Type: GrantFiled: August 29, 2018Date of Patent: November 19, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-hyung Nam, Bong-Soo Kim, Yoosang Hwang
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Publication number: 20190206983Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.Type: ApplicationFiled: August 29, 2018Publication date: July 4, 2019Inventors: Ki-hyung NAM, Bong-Soo KIM, Yoosang HWANG
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Patent number: 9985033Abstract: A semiconductor device including a capacitor is provided. The semiconductor device includes lower electrodes, each of which includes a first electrode and a second electrode stacked in a first direction. The second electrode has a pillar shape that has a bar-type cross section having a longitudinal axis when viewed from a cross-sectional view taken along a plane defined by second and third directions perpendicular to the first direction.Type: GrantFiled: January 4, 2017Date of Patent: May 29, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Taejin Park, Kyung-Eun Kim, Bong-Soo Kim, Ki-hyung Nam, Yoosang Hwang
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Patent number: 9871093Abstract: Provided is a semiconductor device. The semiconductor device includes a capacitor structure including a plurality of lower electrodes, a dielectric layer that covers surfaces of the plurality of lower electrodes, and an upper electrode on the dielectric layer. The semiconductor device further includes a support structure that supports the plurality of lower electrodes. The support structure includes a first support region that covers sidewalls of one of the plurality of lower electrodes, and an opening that envelops the first support region when the semiconductor device is viewed in plan view.Type: GrantFiled: December 19, 2016Date of Patent: January 16, 2018Assignee: Samsung Electonics Co., Ltd.Inventors: Kyung-Eun Kim, Ki-hyung Nam, Byung Yoon Kim, Bong-Soo Kim, Eunjung Kim, Yoosang Hwang
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Publication number: 20170236894Abstract: Provided is a semiconductor device. The semiconductor device includes a capacitor structure including a plurality of lower electrodes, a dielectric layer that covers surfaces of the plurality of lower electrodes, and an upper electrode on the dielectric layer. The semiconductor device further includes a support structure that supports the plurality of lower electrodes. The support structure includes a first support region that covers sidewalls of one of the plurality of lower electrodes, and an opening that envelops the first support region when the semiconductor device is viewed in plan view.Type: ApplicationFiled: December 19, 2016Publication date: August 17, 2017Inventors: Kyung-Eun Kim, Ki-hyung NAM, Byung Yoon KIM, Bong-Soo KIM, Eunjung KIM, Yoosang HWANG
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Publication number: 20170194328Abstract: A semiconductor device including a capacitor is provided. The semiconductor device includes lower electrodes, each of which includes a first electrode and a second electrode stacked in a first direction. The second electrode has a pillar shape that has a bar-type cross section having a longitudinal axis when viewed from a cross-sectional view taken along a plane defined by second and third directions perpendicular to the first direction.Type: ApplicationFiled: January 4, 2017Publication date: July 6, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: TAEJIN PARK, Kyung-Eun KIM, Bong-Soo KIM, Ki-hyung NAM, Yoosang HWANG
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Patent number: 9287160Abstract: A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the device isolation patterns, each of the gate patterns including a gate insulating layer, a gate line and a gate capping pattern, and ohmic patterns on the active portions, respectively. Top surfaces of the first device isolation pattern and the gate insulating layer may be lower than those of the second device isolation pattern and the gate capping pattern, respectively, and the ohmic patterns may include an extending portion on the first insulating layer.Type: GrantFiled: August 14, 2015Date of Patent: March 15, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-hyung Nam, Pulunsol Cho, Yong Kwan Kim
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Publication number: 20150357230Abstract: A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the device isolation patterns, each of the gate patterns including a gate insulating layer, a gate line and a gate capping pattern, and ohmic patterns on the active portions, respectively. Top surfaces of the first device isolation pattern and the gate insulating layer may be lower than those of the second device isolation pattern and the gate capping pattern, respectively, and the ohmic patterns may include an extending portion on the first insulating layer.Type: ApplicationFiled: August 14, 2015Publication date: December 10, 2015Inventors: Ki-hyung NAM, Pulunsol CHO, Yong Kwan KIM
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Patent number: 9166034Abstract: A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the device isolation patterns, each of the gate patterns including a gate insulating layer, a gate line and a gate capping pattern, and ohmic patterns on the active portions, respectively. Top surfaces of the first device isolation pattern and the gate insulating layer may be lower than those of the second device isolation pattern and the gate capping pattern, respectively, and the ohmic patterns may include an extending portion on the first insulating layer.Type: GrantFiled: July 23, 2013Date of Patent: October 20, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-hyung Nam, Pulunsol Cho, Yong Kwan Kim
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Patent number: 8981468Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes active portions defined in a semiconductor substrate, a device isolation pattern in a trench formed between the active portions, a gate electrode in a gate recess region crossing the active portions and the device isolation pattern, a gate dielectric layer between the gate electrode and an inner surface of the gate recess region, and a first ohmic pattern and a second ohmic pattern on each of the active portions at both sides of the gate electrode, respectively. The first and second ohmic patterns include a metal-semiconductor compound, and a top surface of the device isolation pattern at both sides of the gate recess region is recessed to be lower than a level of a top surface of the semiconductor substrate.Type: GrantFiled: July 16, 2013Date of Patent: March 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-hyung Nam, Yong Kwan Kim, Chan Ho Park, Pulunsol Cho
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Patent number: 8901526Abstract: A variable resistive memory device capable of reducing contact resistance by including a contact layer having low contact resistance, the variable resistive memory device including a substrate comprising an active region; a gate line on the substrate; a first contact layer electrically connected to the active region; a memory cell contact plug electrically connected to the first contact layer; and a variable resistive memory cell electrically connected to the memory cell contact plug, wherein the first contact layer has less contact resistance with respect to the active region than the memory cell contact plug.Type: GrantFiled: January 30, 2013Date of Patent: December 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-hyung Nam, Yong-kwan Kim, Ho-joong Lee, Pulunsol Cho
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Publication number: 20140054721Abstract: A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the device isolation patterns, each of the gate patterns including a gate insulating layer, a gate line and a gate capping pattern, and ohmic patterns on the active portions, respectively. Top surfaces of the first device isolation pattern and the gate insulating layer may be lower than those of the second device isolation pattern and the gate capping pattern, respectively, and the ohmic patterns may include an extending portion on the first insulating layer.Type: ApplicationFiled: July 23, 2013Publication date: February 27, 2014Inventors: Ki-hyung NAM, Pulunsol CHO, Yong Kwan KIM