Patents by Inventor Ki-Jae Hur
Ki-Jae Hur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11918978Abstract: Provided is a method of preparing a superabsorbent polymer. More specifically, provided is a method of preparing a superabsorbent polymer capable of exhibiting improved initial absorbency and a rapid absorption rate by polymerizing monomers having acidic groups, of which part is neutralized with a basic material including potassium hydroxide, in the presence of an encapsulated foaming agent.Type: GrantFiled: December 10, 2019Date of Patent: March 5, 2024Assignee: LG Chem, Ltd.Inventors: Seul Ah Lee, Gicheul Kim, Dae Woo Nam, Ki Hyun Kim, Jun Kyu Kim, Young Jae Hur
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Patent number: 10916543Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.Type: GrantFiled: December 24, 2019Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Uk Han, Taek Yong Kim, Satoru Yamada, Jun Hee Lim, Ki Jae Hur
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Patent number: 10770463Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.Type: GrantFiled: June 11, 2019Date of Patent: September 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Hee Cho, Jun Soo Kim, Hui Jung Kim, Tae Yoon An, Satoru Yamada, Won Sok Lee, Nam Ho Jeon, Moon Young Jeong, Ki Jae Hur, Jae Ho Hong
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Publication number: 20200161301Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.Type: ApplicationFiled: December 24, 2019Publication date: May 21, 2020Inventors: Seung Uk Han, Taek Yong Kim, Satoru Yamada, Jun Hee Lim, Ki Jae Hur
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Patent number: 10515962Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.Type: GrantFiled: November 30, 2017Date of Patent: December 24, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Uk Han, Taek Yong Kim, Satoru Yamada, Jun Hee Lim, Ki Jae Hur
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Publication number: 20190296017Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.Type: ApplicationFiled: June 11, 2019Publication date: September 26, 2019Inventors: MIN HEE CHO, JUN SOO KIM, HUI JUNG KIM, TAE YOON AN, SATORU YAMADA, WON SOK LEE, NAM HO JEON, MOON YOUNG JEONG, KI JAE HUR, JAE HO HONG
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Patent number: 10361205Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.Type: GrantFiled: November 22, 2017Date of Patent: July 23, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Hee Cho, Jun Soo Kim, Hui Jung Kim, Tae Yoon An, Satoru Yamada, Won Sok Lee, Nam Ho Jeon, Moon Young Jeong, Ki Jae Hur, Jae Ho Hong
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Publication number: 20180301456Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.Type: ApplicationFiled: November 22, 2017Publication date: October 18, 2018Inventors: Min Hee Cho, Jun Soo Kim, Hui Jung Kim, Tae Yoon An, Satoru Yamada, Won Sok Lee, Nam Ho Jeon, Moon Young Jeong, Ki Jae Hur, Jae Ho Hong
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Publication number: 20180294264Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.Type: ApplicationFiled: November 30, 2017Publication date: October 11, 2018Inventors: Seung Uk Han, Taek Yong Kim, Satoru Yamada, Jun Hee Lim, Ki Jae Hur
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Patent number: 9484203Abstract: In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An ion implantation process is performed at an upper portion of the substrate exposed by the gate structure, so that an ion implantation region is formed to have an expanded volume. The ion implantation process uses ions that are identical to a material of the substrate.Type: GrantFiled: November 7, 2014Date of Patent: November 1, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-Hee Lim, Ki-Jae Hur, Sung-Hwan Kim, Hae-In Jung, Soo-Jin Hong
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Patent number: 9269810Abstract: A semiconductor device includes an active region defined on a substrate, a gate electrode disposed on the active region and covering two adjacent corners of the active region, a drain area formed in the active region adjacent to a first side of the gate electrode, and a source area formed in the active region adjacent to a second side of the gate electrode. The first and second sides of the gate electrode are spaced apart from each other, and the first side has a bent shape.Type: GrantFiled: July 28, 2014Date of Patent: February 23, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Uk Han, Won-Kyung Park, Jun-Ho Park, Jun-Hee Lim, Ki-Jae Hur
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Patent number: 9240415Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.Type: GrantFiled: June 24, 2014Date of Patent: January 19, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won-Kyung Park, Ki-Jae Hur, Hyeong-Sun Hong, Se-Young Kim, Jun-Hee Lim
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Publication number: 20150235852Abstract: In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An ion implantation process is performed at an upper portion of the substrate exposed by the gate structure, so that an ion implantation region is formed to have an expanded volume. The ion implantation process uses ions that are identical to a material of the substrate.Type: ApplicationFiled: November 7, 2014Publication date: August 20, 2015Inventors: Jun-Hee LIM, Ki-Jae HUR, Sung-Hwan KIM, Hae-In JUNG, Soo-Jin HONG
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Publication number: 20150171215Abstract: A semiconductor device includes an active region defined on a substrate, a gate electrode disposed on the active region and covering two adjacent corners of the active region, a drain area formed in the active region adjacent to a first side of the gate electrode, and a source area formed in the active region adjacent to a second side of the gate electrode. The first and second sides of the gate electrode are spaced apart from each other, and the first side has a bent shape.Type: ApplicationFiled: July 28, 2014Publication date: June 18, 2015Inventors: Seung-uk HAN, Won-kyung PARK, Jun-ho PARK, Jun-hee LIM, Ki-jae HUR
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Publication number: 20150008530Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.Type: ApplicationFiled: June 24, 2014Publication date: January 8, 2015Inventors: Won-Kyung Park, Ki-Jae Hur, Hyeong-Sun Hong, Se-Young Kim, Jun-Hee Lim
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Patent number: 7786517Abstract: A semiconductor device and method of forming the same are provided. The example semiconductor device may include a gate pattern including a gate electrode and a capping layer pattern on a semiconductor substrate, a spacer covering first and second sidewalls of the gate pattern, an impurity injection region formed in the semiconductor substrate adjacent to the gate pattern and an etch stopping layer covering a surface of the semiconductor substrate adjacent to the spacer, the etch stopping layer substantially not covering the first and second sidewalls of the spacer and an upper surface of the capping layer pattern.Type: GrantFiled: April 17, 2007Date of Patent: August 31, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Ki-Jae Hur
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Publication number: 20080272430Abstract: A semiconductor device includes an active region defined in a substrate, the active region having a trench extending below a surface of the substrate; an impurity region provided along a bottom surface and a lower sidewall of the trench, wherein an upper portion of the impurity region is spaced apart from the surface of the substrate and an upper portion of the trench; a gate insulating layer provided along an inner surface of the trench; and a gate electrode provided in the trench.Type: ApplicationFiled: April 28, 2008Publication date: November 6, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-Jae Hur, Jun-Hee Lim, Hyuck-Chai Jung
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Patent number: 7442613Abstract: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.Type: GrantFiled: October 25, 2006Date of Patent: October 28, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Jae Hur, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
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Publication number: 20070278599Abstract: A semiconductor device and method of forming the same are provided. The example semiconductor device may include a gate pattern including a gate electrode and a capping layer pattern on a semiconductor substrate, a spacer covering first and second sidewalls of the gate pattern, an impurity injection region formed in the semiconductor substrate adjacent to the gate pattern and an etch stopping layer covering a surface of the semiconductor substrate adjacent to the spacer, the etch stopping layer substantially not covering the first and second sidewalls of the spacer and an upper surface of the capping layer pattern.Type: ApplicationFiled: April 17, 2007Publication date: December 6, 2007Inventor: Ki-Jae Hur
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Publication number: 20070102785Abstract: A semiconductor device having a fuse and a method of fabricating the same are provided. An embodiment of he semiconductor device includes a fuse pattern having a fuse conductive pattern disposed on a semiconductor substrate and a fuse capping pattern disposed on the fuse conductive pattern. An upper insulating layer is formed to cover the semiconductor substrate having the fuse pattern. A fuse window exposing the fuse pattern through the upper insulating layer is formed. A fuse spacer and a fuse window spacer are disposed on sidewalls of the fuse pattern exposed by the fuse window and sidewalls of the fuse window, respectively.Type: ApplicationFiled: November 6, 2006Publication date: May 10, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Ki-Jae HUR