Patents by Inventor Ki Jun BANG

Ki Jun BANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor devices including redistributed layer structures and methods of forming semiconductor devices including redistributed layer structures
    Patent number: 10998266
    Abstract: A semiconductor device includes a semiconductor chip body having a surface on which a chip pad is disposed, a passivation layer covering the surface of the semiconductor chip body and providing a tapered hole revealing the chip pad, and a redistributed layer (RDL) structure disposed on the passivation layer. The RDL structure includes a first RDL interconnection portion spaced apart from the tapered hole and passing by the tapered hole and a second RDL overlapping pad portion configured to have a bottom portion contacting the revealed chip pad and configured to have a first side surface facing a side surface of the first RDL interconnection portion. A central portion of the first side surface of the second RDL overlapping pad portion extends toward the side surface of the first RDL interconnection portion such that the first side surface is curved.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Bang, Sang Jae Kim, Shin Young Park
  • SEMICONDUCTOR DEVICES INCLUDING REDISTRIBUTED LAYER STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING REDISTRIBUTED LAYER STRUCTURES
    Publication number: 20200118918
    Abstract: A semiconductor device includes a semiconductor chip body having a surface on which a chip pad is disposed, a passivation layer covering the surface of the semiconductor chip body and providing a tapered hole revealing the chip pad, and a redistributed layer (RDL) structure disposed on the passivation layer. The RDL structure includes a first RDL interconnection portion spaced apart from the tapered hole and passing by the tapered hole and a second RDL overlapping pad portion configured to have a bottom portion contacting the revealed chip pad and configured to have a first side surface facing a side surface of the first RDL interconnection portion. A central portion of the first side surface of the second RDL overlapping pad portion extends toward the side surface of the first RDL interconnection portion such that the first side surface is curved.
    Type: Application
    Filed: December 14, 2018
    Publication date: April 16, 2020
    Applicant: SK hynix Inc.
    Inventors: Ki Jun BANG, Sang Jae KIM, Shin Young PARK