Abstract: A semiconductor test system capable of performing a virtual test and a semiconductor test method thereof. The semiconductor test system includes a tester providing a test signal and an emulator providing a virtual test result to the tester in response to the test signal. The emulator includes virtual prober software to obtain the virtual test result.

Abstract: A method for testing a semiconductor device includes generating chip identification data for each of a plurality of devices under test to collect a plurality of chip identification data respectively corresponding to the plurality of devices under test. The plurality of chip identification data for the plurality of devices under test is transmitted responsive to collection thereof. The plurality of chip identification data may be received and written in parallel to the corresponding ones of the plurality of devices under test. Related apparatus are also discussed.

Abstract: An apparatus for testing a semiconductor device includes: a power supplying unit for generating a voltage to be supplied to the semiconductor device under control of a test controller; a voltage transmitting unit for transmitting the voltage to the semiconductor device under control of the test controller; and an overcurrent detecting unit for detecting whether an overcurrent is supplied from an output of the power supplying unit, wherein the voltage transmitting unit cuts off a voltage supply to the semiconductor device in response to an output of the overcurrent detecting unit without intervention of the test controller.

Abstract: A test system that tests first through m-th circuit devices for defects. The test system includes a controller and first through m-th control circuits. The controller is configured to generate a test signal having information for testing first through m-th circuit devices. The first through m-th control circuits are each configured to test a respective one of the first through m-th circuit devices for a defect using the test signal, and to stop testing the respective one of the first through m-th circuit devices when a defect is identified.

Abstract: A test apparatus simultaneously tests a plurality of semiconductor integrated circuits according to test data stored in a single memory set. A sub-test data generator includes a plurality of data reproduction units, each of which corresponds to one of the integrated circuits being tested. Each data reproduction unit reproduces the stored test data into a reproduced test data set, which is then processed by a driver, and sent to the corresponding integrated circuit for testing.

Abstract: A test system that tests first through m-th circuit devices for defects. The test system includes a controller and first through m-th control circuits. The controller is configured to generate a test signal having information for testing first through m-th circuit devices. The first through m-th control circuits are each configured to test a respective one of the first through m-th circuit devices for a defect using the test signal, and to stop testing the respective one of the first through m-th circuit devices when a defect is identified.

Abstract: A test apparatus simultaneously tests a plurality of semiconductor integrated circuits according to test data stored in a single memory set. A sub-test data generator includes a plurality of data reproduction units, each of which corresponds to one of the integrated circuits being tested. Each data reproduction unit reproduces the stored test data into a reproduced test data set, which is then processed by a driver, and sent to the corresponding integrated circuit for testing.